b9fc6b56f4
This patch implements irq_set_vcpu_affinity() function to set up interrupt remapping table entry with vapic mode for pass-through devices. In case requirements for vapic mode are not met, it falls back to set up the IRTE in legacy mode. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
215 lines
6.8 KiB
C
215 lines
6.8 KiB
C
/*
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* Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <joerg.roedel@amd.com>
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* Leo Duran <leo.duran@amd.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ASM_X86_AMD_IOMMU_H
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#define _ASM_X86_AMD_IOMMU_H
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#include <linux/types.h>
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/*
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* This is mainly used to communicate information back-and-forth
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* between SVM and IOMMU for setting up and tearing down posted
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* interrupt
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*/
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struct amd_iommu_pi_data {
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u32 ga_tag;
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u32 prev_ga_tag;
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u64 base;
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bool is_guest_mode;
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struct vcpu_data *vcpu_data;
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void *ir_data;
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};
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#ifdef CONFIG_AMD_IOMMU
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struct task_struct;
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struct pci_dev;
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extern int amd_iommu_detect(void);
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extern int amd_iommu_init_hardware(void);
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/**
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* amd_iommu_enable_device_erratum() - Enable erratum workaround for device
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* in the IOMMUv2 driver
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* @pdev: The PCI device the workaround is necessary for
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* @erratum: The erratum workaround to enable
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*
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* The function needs to be called before amd_iommu_init_device().
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* Possible values for the erratum number are for now:
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* - AMD_PRI_DEV_ERRATUM_ENABLE_RESET - Reset PRI capability when PRI
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* is enabled
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* - AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE - Limit number of outstanding PRI
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* requests to one
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*/
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#define AMD_PRI_DEV_ERRATUM_ENABLE_RESET 0
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#define AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE 1
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extern void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum);
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/**
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* amd_iommu_init_device() - Init device for use with IOMMUv2 driver
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* @pdev: The PCI device to initialize
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* @pasids: Number of PASIDs to support for this device
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*
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* This function does all setup for the device pdev so that it can be
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* used with IOMMUv2.
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* Returns 0 on success or negative value on error.
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*/
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extern int amd_iommu_init_device(struct pci_dev *pdev, int pasids);
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/**
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* amd_iommu_free_device() - Free all IOMMUv2 related device resources
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* and disable IOMMUv2 usage for this device
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* @pdev: The PCI device to disable IOMMUv2 usage for'
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*/
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extern void amd_iommu_free_device(struct pci_dev *pdev);
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/**
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* amd_iommu_bind_pasid() - Bind a given task to a PASID on a device
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* @pdev: The PCI device to bind the task to
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* @pasid: The PASID on the device the task should be bound to
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* @task: the task to bind
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*
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* The function returns 0 on success or a negative value on error.
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*/
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extern int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid,
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struct task_struct *task);
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/**
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* amd_iommu_unbind_pasid() - Unbind a PASID from its task on
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* a device
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* @pdev: The device of the PASID
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* @pasid: The PASID to unbind
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*
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* When this function returns the device is no longer using the PASID
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* and the PASID is no longer bound to its task.
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*/
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extern void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid);
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/**
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* amd_iommu_set_invalid_ppr_cb() - Register a call-back for failed
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* PRI requests
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* @pdev: The PCI device the call-back should be registered for
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* @cb: The call-back function
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*
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* The IOMMUv2 driver invokes this call-back when it is unable to
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* successfully handle a PRI request. The device driver can then decide
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* which PRI response the device should see. Possible return values for
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* the call-back are:
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*
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* - AMD_IOMMU_INV_PRI_RSP_SUCCESS - Send SUCCESS back to the device
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* - AMD_IOMMU_INV_PRI_RSP_INVALID - Send INVALID back to the device
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* - AMD_IOMMU_INV_PRI_RSP_FAIL - Send Failure back to the device,
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* the device is required to disable
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* PRI when it receives this response
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*
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* The function returns 0 on success or negative value on error.
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*/
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#define AMD_IOMMU_INV_PRI_RSP_SUCCESS 0
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#define AMD_IOMMU_INV_PRI_RSP_INVALID 1
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#define AMD_IOMMU_INV_PRI_RSP_FAIL 2
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typedef int (*amd_iommu_invalid_ppr_cb)(struct pci_dev *pdev,
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int pasid,
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unsigned long address,
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u16);
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extern int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
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amd_iommu_invalid_ppr_cb cb);
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#define PPR_FAULT_EXEC (1 << 1)
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#define PPR_FAULT_READ (1 << 2)
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#define PPR_FAULT_WRITE (1 << 5)
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#define PPR_FAULT_USER (1 << 6)
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#define PPR_FAULT_RSVD (1 << 7)
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#define PPR_FAULT_GN (1 << 8)
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/**
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* amd_iommu_device_info() - Get information about IOMMUv2 support of a
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* PCI device
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* @pdev: PCI device to query information from
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* @info: A pointer to an amd_iommu_device_info structure which will contain
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* the information about the PCI device
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*
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* Returns 0 on success, negative value on error
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*/
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#define AMD_IOMMU_DEVICE_FLAG_ATS_SUP 0x1 /* ATS feature supported */
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#define AMD_IOMMU_DEVICE_FLAG_PRI_SUP 0x2 /* PRI feature supported */
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#define AMD_IOMMU_DEVICE_FLAG_PASID_SUP 0x4 /* PASID context supported */
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#define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP 0x8 /* Device may request execution
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on memory pages */
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#define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP 0x10 /* Device may request
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super-user privileges */
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struct amd_iommu_device_info {
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int max_pasids;
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u32 flags;
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};
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extern int amd_iommu_device_info(struct pci_dev *pdev,
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struct amd_iommu_device_info *info);
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/**
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* amd_iommu_set_invalidate_ctx_cb() - Register a call-back for invalidating
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* a pasid context. This call-back is
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* invoked when the IOMMUv2 driver needs to
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* invalidate a PASID context, for example
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* because the task that is bound to that
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* context is about to exit.
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*
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* @pdev: The PCI device the call-back should be registered for
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* @cb: The call-back function
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*/
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typedef void (*amd_iommu_invalidate_ctx)(struct pci_dev *pdev, int pasid);
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extern int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
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amd_iommu_invalidate_ctx cb);
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#else /* CONFIG_AMD_IOMMU */
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static inline int amd_iommu_detect(void) { return -ENODEV; }
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#endif /* CONFIG_AMD_IOMMU */
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#if defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP)
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/* IOMMU AVIC Function */
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extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32));
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extern int
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amd_iommu_update_ga(int cpu, bool is_run, void *data);
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#else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
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static inline int
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amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
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{
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return 0;
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}
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static inline int
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amd_iommu_update_ga(int cpu, bool is_run, void *data)
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{
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return 0;
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}
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#endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
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#endif /* _ASM_X86_AMD_IOMMU_H */
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