d892c9f357
Currently, PWM core driver provides interfaces for configuring PWM
period and duty length in nanoseconds with an integer data type, so
the max period can be only set to ~2.147 seconds. Add interfaces which
can set PWM period and duty with u64 data type to remove this
limitation.
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
Bug: 152542675
Test: build and boot
(cherry picked from commit a691c36aef)
[surenb: removed sysfs API changes, replaced 32-bit divisions with 64-bit
ones in the following drivers to fix allmodconfig build:
drivers/clk/clk-pwm.c
drivers/hwmon/pwm-fan.c
drivers/pwm/pwm-clps711x.c
drivers/pwm/pwm-sti.c
drivers/pwm/pwm-sun4i.c
]
Signed-off-by: Suren Baghdasaryan <surenb@google.com>
Change-Id: I149c14b2d59b181344e7bb77393c64bcd9998de5
Merged-In: I149c14b2d59b181344e7bb77393c64bcd9998de5
142 lines
3.3 KiB
C
142 lines
3.3 KiB
C
/*
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* Copyright (C) 2014 Philipp Zabel, Pengutronix
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* PWM (mis)used as clock output
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*/
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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struct clk_pwm {
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struct clk_hw hw;
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struct pwm_device *pwm;
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u32 fixed_rate;
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};
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static inline struct clk_pwm *to_clk_pwm(struct clk_hw *hw)
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{
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return container_of(hw, struct clk_pwm, hw);
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}
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static int clk_pwm_prepare(struct clk_hw *hw)
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{
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struct clk_pwm *clk_pwm = to_clk_pwm(hw);
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return pwm_enable(clk_pwm->pwm);
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}
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static void clk_pwm_unprepare(struct clk_hw *hw)
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{
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struct clk_pwm *clk_pwm = to_clk_pwm(hw);
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pwm_disable(clk_pwm->pwm);
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}
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static unsigned long clk_pwm_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_pwm *clk_pwm = to_clk_pwm(hw);
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return clk_pwm->fixed_rate;
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}
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static const struct clk_ops clk_pwm_ops = {
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.prepare = clk_pwm_prepare,
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.unprepare = clk_pwm_unprepare,
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.recalc_rate = clk_pwm_recalc_rate,
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};
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static int clk_pwm_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_init_data init = {};
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struct clk_pwm *clk_pwm;
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struct pwm_device *pwm;
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struct pwm_args pargs;
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const char *clk_name;
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int ret;
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clk_pwm = devm_kzalloc(&pdev->dev, sizeof(*clk_pwm), GFP_KERNEL);
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if (!clk_pwm)
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return -ENOMEM;
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pwm = devm_pwm_get(&pdev->dev, NULL);
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if (IS_ERR(pwm))
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return PTR_ERR(pwm);
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pwm_get_args(pwm, &pargs);
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if (!pargs.period) {
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dev_err(&pdev->dev, "invalid PWM period\n");
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return -EINVAL;
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}
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if (of_property_read_u32(node, "clock-frequency", &clk_pwm->fixed_rate))
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clk_pwm->fixed_rate = div64_u64(NSEC_PER_SEC, pargs.period);
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if (pargs.period != NSEC_PER_SEC / clk_pwm->fixed_rate &&
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pargs.period != DIV_ROUND_UP(NSEC_PER_SEC, clk_pwm->fixed_rate)) {
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dev_err(&pdev->dev,
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"clock-frequency does not match PWM period\n");
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return -EINVAL;
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}
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/*
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* FIXME: pwm_apply_args() should be removed when switching to the
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* atomic PWM API.
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*/
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pwm_apply_args(pwm);
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ret = pwm_config(pwm, (pargs.period + 1) >> 1, pargs.period);
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if (ret < 0)
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return ret;
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clk_name = node->name;
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of_property_read_string(node, "clock-output-names", &clk_name);
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init.name = clk_name;
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init.ops = &clk_pwm_ops;
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init.flags = CLK_IS_BASIC;
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init.num_parents = 0;
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clk_pwm->pwm = pwm;
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clk_pwm->hw.init = &init;
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ret = devm_clk_hw_register(&pdev->dev, &clk_pwm->hw);
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if (ret)
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return ret;
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return of_clk_add_hw_provider(node, of_clk_hw_simple_get, &clk_pwm->hw);
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}
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static int clk_pwm_remove(struct platform_device *pdev)
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{
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of_clk_del_provider(pdev->dev.of_node);
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return 0;
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}
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static const struct of_device_id clk_pwm_dt_ids[] = {
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{ .compatible = "pwm-clock" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, clk_pwm_dt_ids);
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static struct platform_driver clk_pwm_driver = {
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.probe = clk_pwm_probe,
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.remove = clk_pwm_remove,
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.driver = {
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.name = "pwm-clock",
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.of_match_table = of_match_ptr(clk_pwm_dt_ids),
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},
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};
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module_platform_driver(clk_pwm_driver);
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MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
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MODULE_DESCRIPTION("PWM clock driver");
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MODULE_LICENSE("GPL");
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