591d14f007
When using an rbtree cache, there can be allocations the first time a register is accessed. This can cause an attempt to schedule while atomic in the case that the regmap is using a spinlock. This could be fixed by either initializing all the registers or using a flat cache. The register maps for tegra30_ahub and tegra30_i2s are dense and don't save much from using a tree so convert them to flat. Tegra30 changes tested on Norrin, Tegra20 changes compile. Signed-off-by: Dylan Reid <dgreid@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>
246 lines
5.8 KiB
C
246 lines
5.8 KiB
C
/*
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* tegra20_das.c - Tegra20 DAS driver
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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* Copyright (C) 2010 - NVIDIA, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <sound/soc.h>
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#include "tegra20_das.h"
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#define DRV_NAME "tegra20-das"
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static struct tegra20_das *das;
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static inline void tegra20_das_write(u32 reg, u32 val)
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{
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regmap_write(das->regmap, reg, val);
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}
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static inline u32 tegra20_das_read(u32 reg)
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{
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u32 val;
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regmap_read(das->regmap, reg, &val);
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return val;
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}
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int tegra20_das_connect_dap_to_dac(int dap, int dac)
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{
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u32 addr;
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u32 reg;
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if (!das)
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return -ENODEV;
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addr = TEGRA20_DAS_DAP_CTRL_SEL +
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(dap * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
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reg = dac << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P;
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tegra20_das_write(addr, reg);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra20_das_connect_dap_to_dac);
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int tegra20_das_connect_dap_to_dap(int dap, int otherdap, int master,
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int sdata1rx, int sdata2rx)
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{
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u32 addr;
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u32 reg;
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if (!das)
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return -ENODEV;
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addr = TEGRA20_DAS_DAP_CTRL_SEL +
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(dap * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
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reg = otherdap << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P |
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!!sdata2rx << TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P |
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!!sdata1rx << TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P |
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!!master << TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P;
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tegra20_das_write(addr, reg);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra20_das_connect_dap_to_dap);
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int tegra20_das_connect_dac_to_dap(int dac, int dap)
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{
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u32 addr;
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u32 reg;
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if (!das)
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return -ENODEV;
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addr = TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL +
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(dac * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE);
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reg = dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P |
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dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P |
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dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P;
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tegra20_das_write(addr, reg);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra20_das_connect_dac_to_dap);
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#define LAST_REG(name) \
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(TEGRA20_DAS_##name + \
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(TEGRA20_DAS_##name##_STRIDE * (TEGRA20_DAS_##name##_COUNT - 1)))
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static bool tegra20_das_wr_rd_reg(struct device *dev, unsigned int reg)
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{
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if ((reg >= TEGRA20_DAS_DAP_CTRL_SEL) &&
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(reg <= LAST_REG(DAP_CTRL_SEL)))
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return true;
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if ((reg >= TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL) &&
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(reg <= LAST_REG(DAC_INPUT_DATA_CLK_SEL)))
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return true;
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return false;
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}
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static const struct regmap_config tegra20_das_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = LAST_REG(DAC_INPUT_DATA_CLK_SEL),
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.writeable_reg = tegra20_das_wr_rd_reg,
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.readable_reg = tegra20_das_wr_rd_reg,
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.cache_type = REGCACHE_FLAT,
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};
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static int tegra20_das_probe(struct platform_device *pdev)
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{
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struct resource *res, *region;
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void __iomem *regs;
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int ret = 0;
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if (das)
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return -ENODEV;
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das = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_das), GFP_KERNEL);
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if (!das) {
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dev_err(&pdev->dev, "Can't allocate tegra20_das\n");
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ret = -ENOMEM;
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goto err;
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}
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das->dev = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "No memory resource\n");
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ret = -ENODEV;
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goto err;
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}
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region = devm_request_mem_region(&pdev->dev, res->start,
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resource_size(res), pdev->name);
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if (!region) {
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dev_err(&pdev->dev, "Memory region already claimed\n");
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ret = -EBUSY;
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goto err;
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}
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regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
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if (!regs) {
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dev_err(&pdev->dev, "ioremap failed\n");
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ret = -ENOMEM;
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goto err;
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}
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das->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
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&tegra20_das_regmap_config);
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if (IS_ERR(das->regmap)) {
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dev_err(&pdev->dev, "regmap init failed\n");
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ret = PTR_ERR(das->regmap);
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goto err;
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}
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ret = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_1,
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TEGRA20_DAS_DAP_SEL_DAC1);
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if (ret) {
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dev_err(&pdev->dev, "Can't set up DAS DAP connection\n");
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goto err;
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}
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ret = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAC_ID_1,
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TEGRA20_DAS_DAC_SEL_DAP1);
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if (ret) {
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dev_err(&pdev->dev, "Can't set up DAS DAC connection\n");
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goto err;
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}
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ret = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_3,
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TEGRA20_DAS_DAP_SEL_DAC3);
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if (ret) {
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dev_err(&pdev->dev, "Can't set up DAS DAP connection\n");
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goto err;
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}
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ret = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAC_ID_3,
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TEGRA20_DAS_DAC_SEL_DAP3);
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if (ret) {
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dev_err(&pdev->dev, "Can't set up DAS DAC connection\n");
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goto err;
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}
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platform_set_drvdata(pdev, das);
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return 0;
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err:
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das = NULL;
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return ret;
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}
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static int tegra20_das_remove(struct platform_device *pdev)
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{
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if (!das)
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return -ENODEV;
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das = NULL;
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return 0;
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}
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static const struct of_device_id tegra20_das_of_match[] = {
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{ .compatible = "nvidia,tegra20-das", },
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{},
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};
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static struct platform_driver tegra20_das_driver = {
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.probe = tegra20_das_probe,
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.remove = tegra20_das_remove,
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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.of_match_table = tegra20_das_of_match,
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},
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};
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module_platform_driver(tegra20_das_driver);
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MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
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MODULE_DESCRIPTION("Tegra20 DAS driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:" DRV_NAME);
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MODULE_DEVICE_TABLE(of, tegra20_das_of_match);
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