f6365201d8
The X86_32-only disable_hlt/enable_hlt mechanism was used by the 32-bit floppy driver. Its effect was to replace the use of the HLT instruction inside default_idle() with cpu_relax() - essentially it turned off the use of HLT. This workaround was commented in the code as: "disable hlt during certain critical i/o operations" "This halt magic was a workaround for ancient floppy DMA wreckage. It should be safe to remove." H. Peter Anvin additionally adds: "To the best of my knowledge, no-hlt only existed because of flaky power distributions on 386/486 systems which were sold to run DOS. Since DOS did no power management of any kind, including HLT, the power draw was fairly uniform; when exposed to the much hhigher noise levels you got when Linux used HLT caused some of these systems to fail. They were by far in the minority even back then." Alan Cox further says: "Also for the Cyrix 5510 which tended to go castors up if a HLT occurred during a DMA cycle and on a few other boxes HLT during DMA tended to go astray. Do we care ? I doubt it. The 5510 was pretty obscure, the 5520 fixed it, the 5530 is probably the oldest still in any kind of use." So, let's finally drop this. Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Josh Boyer <jwboyer@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Acked-by: "H. Peter Anvin" <hpa@zytor.com> Acked-by: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Stephen Hemminger <shemminger@vyatta.com Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: <stable@kernel.org> Link: http://lkml.kernel.org/n/tip-3rhk9bzf0x9rljkv488tloib@git.kernel.org [ If anyone cares then alternative instruction patching could be used to replace HLT with a one-byte NOP instruction. Much simpler. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
758 lines
18 KiB
C
758 lines
18 KiB
C
#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/prctl.h>
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#include <linux/slab.h>
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#include <linux/sched.h>
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#include <linux/module.h>
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#include <linux/pm.h>
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#include <linux/clockchips.h>
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#include <linux/random.h>
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#include <linux/user-return-notifier.h>
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#include <linux/dmi.h>
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#include <linux/utsname.h>
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#include <linux/stackprotector.h>
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#include <linux/tick.h>
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#include <linux/cpuidle.h>
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#include <trace/events/power.h>
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#include <linux/hw_breakpoint.h>
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#include <asm/cpu.h>
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#include <asm/apic.h>
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#include <asm/syscalls.h>
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#include <asm/idle.h>
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#include <asm/uaccess.h>
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#include <asm/i387.h>
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#include <asm/fpu-internal.h>
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#include <asm/debugreg.h>
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#include <asm/nmi.h>
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#ifdef CONFIG_X86_64
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static DEFINE_PER_CPU(unsigned char, is_idle);
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static ATOMIC_NOTIFIER_HEAD(idle_notifier);
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void idle_notifier_register(struct notifier_block *n)
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{
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atomic_notifier_chain_register(&idle_notifier, n);
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}
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EXPORT_SYMBOL_GPL(idle_notifier_register);
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void idle_notifier_unregister(struct notifier_block *n)
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{
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atomic_notifier_chain_unregister(&idle_notifier, n);
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}
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EXPORT_SYMBOL_GPL(idle_notifier_unregister);
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#endif
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struct kmem_cache *task_xstate_cachep;
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EXPORT_SYMBOL_GPL(task_xstate_cachep);
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int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
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{
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int ret;
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*dst = *src;
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if (fpu_allocated(&src->thread.fpu)) {
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memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
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ret = fpu_alloc(&dst->thread.fpu);
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if (ret)
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return ret;
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fpu_copy(&dst->thread.fpu, &src->thread.fpu);
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}
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return 0;
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}
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void free_thread_xstate(struct task_struct *tsk)
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{
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fpu_free(&tsk->thread.fpu);
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}
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void free_thread_info(struct thread_info *ti)
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{
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free_thread_xstate(ti->task);
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free_pages((unsigned long)ti, THREAD_ORDER);
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}
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void arch_task_cache_init(void)
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{
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task_xstate_cachep =
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kmem_cache_create("task_xstate", xstate_size,
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__alignof__(union thread_xstate),
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SLAB_PANIC | SLAB_NOTRACK, NULL);
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}
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/*
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* Free current thread data structures etc..
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*/
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void exit_thread(void)
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{
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struct task_struct *me = current;
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struct thread_struct *t = &me->thread;
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unsigned long *bp = t->io_bitmap_ptr;
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if (bp) {
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struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
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t->io_bitmap_ptr = NULL;
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clear_thread_flag(TIF_IO_BITMAP);
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/*
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* Careful, clear this in the TSS too:
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*/
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memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
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t->io_bitmap_max = 0;
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put_cpu();
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kfree(bp);
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}
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}
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void show_regs(struct pt_regs *regs)
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{
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show_registers(regs);
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show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs), 0);
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}
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void show_regs_common(void)
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{
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const char *vendor, *product, *board;
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vendor = dmi_get_system_info(DMI_SYS_VENDOR);
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if (!vendor)
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vendor = "";
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product = dmi_get_system_info(DMI_PRODUCT_NAME);
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if (!product)
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product = "";
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/* Board Name is optional */
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board = dmi_get_system_info(DMI_BOARD_NAME);
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printk(KERN_CONT "\n");
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printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s",
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current->pid, current->comm, print_tainted(),
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init_utsname()->release,
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(int)strcspn(init_utsname()->version, " "),
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init_utsname()->version);
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printk(KERN_CONT " %s %s", vendor, product);
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if (board)
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printk(KERN_CONT "/%s", board);
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printk(KERN_CONT "\n");
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}
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void flush_thread(void)
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{
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struct task_struct *tsk = current;
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flush_ptrace_hw_breakpoint(tsk);
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memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
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/*
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* Forget coprocessor state..
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*/
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tsk->fpu_counter = 0;
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clear_fpu(tsk);
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clear_used_math();
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}
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static void hard_disable_TSC(void)
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{
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write_cr4(read_cr4() | X86_CR4_TSD);
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}
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void disable_TSC(void)
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{
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preempt_disable();
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if (!test_and_set_thread_flag(TIF_NOTSC))
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/*
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* Must flip the CPU state synchronously with
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* TIF_NOTSC in the current running context.
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*/
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hard_disable_TSC();
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preempt_enable();
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}
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static void hard_enable_TSC(void)
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{
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write_cr4(read_cr4() & ~X86_CR4_TSD);
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}
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static void enable_TSC(void)
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{
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preempt_disable();
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if (test_and_clear_thread_flag(TIF_NOTSC))
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/*
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* Must flip the CPU state synchronously with
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* TIF_NOTSC in the current running context.
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*/
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hard_enable_TSC();
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preempt_enable();
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}
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int get_tsc_mode(unsigned long adr)
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{
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unsigned int val;
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if (test_thread_flag(TIF_NOTSC))
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val = PR_TSC_SIGSEGV;
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else
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val = PR_TSC_ENABLE;
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return put_user(val, (unsigned int __user *)adr);
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}
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int set_tsc_mode(unsigned int val)
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{
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if (val == PR_TSC_SIGSEGV)
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disable_TSC();
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else if (val == PR_TSC_ENABLE)
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enable_TSC();
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else
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return -EINVAL;
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return 0;
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}
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void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
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struct tss_struct *tss)
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{
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struct thread_struct *prev, *next;
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prev = &prev_p->thread;
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next = &next_p->thread;
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if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
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test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
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unsigned long debugctl = get_debugctlmsr();
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debugctl &= ~DEBUGCTLMSR_BTF;
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if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
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debugctl |= DEBUGCTLMSR_BTF;
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update_debugctlmsr(debugctl);
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}
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if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
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test_tsk_thread_flag(next_p, TIF_NOTSC)) {
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/* prev and next are different */
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if (test_tsk_thread_flag(next_p, TIF_NOTSC))
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hard_disable_TSC();
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else
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hard_enable_TSC();
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}
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if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
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/*
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* Copy the relevant range of the IO bitmap.
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* Normally this is 128 bytes or less:
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*/
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memcpy(tss->io_bitmap, next->io_bitmap_ptr,
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max(prev->io_bitmap_max, next->io_bitmap_max));
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} else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
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/*
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* Clear any possible leftover bits:
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*/
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memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
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}
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propagate_user_return_notify(prev_p, next_p);
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}
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int sys_fork(struct pt_regs *regs)
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{
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return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
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}
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/*
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* This is trivial, and on the face of it looks like it
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* could equally well be done in user mode.
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*
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* Not so, for quite unobvious reasons - register pressure.
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* In user mode vfork() cannot have a stack frame, and if
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* done by calling the "clone()" system call directly, you
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* do not have enough call-clobbered registers to hold all
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* the information you need.
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*/
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int sys_vfork(struct pt_regs *regs)
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{
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return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
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NULL, NULL);
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}
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long
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sys_clone(unsigned long clone_flags, unsigned long newsp,
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void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
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{
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if (!newsp)
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newsp = regs->sp;
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return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
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}
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/*
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* This gets run with %si containing the
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* function to call, and %di containing
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* the "args".
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*/
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extern void kernel_thread_helper(void);
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/*
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* Create a kernel thread
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*/
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int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
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{
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struct pt_regs regs;
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memset(®s, 0, sizeof(regs));
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regs.si = (unsigned long) fn;
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regs.di = (unsigned long) arg;
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#ifdef CONFIG_X86_32
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regs.ds = __USER_DS;
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regs.es = __USER_DS;
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regs.fs = __KERNEL_PERCPU;
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regs.gs = __KERNEL_STACK_CANARY;
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#else
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regs.ss = __KERNEL_DS;
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#endif
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regs.orig_ax = -1;
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regs.ip = (unsigned long) kernel_thread_helper;
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regs.cs = __KERNEL_CS | get_kernel_rpl();
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regs.flags = X86_EFLAGS_IF | X86_EFLAGS_BIT1;
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/* Ok, create the new process.. */
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return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
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}
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EXPORT_SYMBOL(kernel_thread);
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/*
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* sys_execve() executes a new program.
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*/
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long sys_execve(const char __user *name,
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const char __user *const __user *argv,
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const char __user *const __user *envp, struct pt_regs *regs)
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{
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long error;
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char *filename;
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filename = getname(name);
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error = PTR_ERR(filename);
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if (IS_ERR(filename))
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return error;
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error = do_execve(filename, argv, envp, regs);
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#ifdef CONFIG_X86_32
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if (error == 0) {
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/* Make sure we don't return using sysenter.. */
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set_thread_flag(TIF_IRET);
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}
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#endif
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putname(filename);
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return error;
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}
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/*
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* Idle related variables and functions
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*/
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unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
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EXPORT_SYMBOL(boot_option_idle_override);
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/*
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* Powermanagement idle function, if any..
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*/
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void (*pm_idle)(void);
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#ifdef CONFIG_APM_MODULE
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EXPORT_SYMBOL(pm_idle);
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#endif
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static inline int hlt_use_halt(void)
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{
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return 1;
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}
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#ifndef CONFIG_SMP
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static inline void play_dead(void)
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{
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BUG();
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}
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#endif
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#ifdef CONFIG_X86_64
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void enter_idle(void)
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{
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percpu_write(is_idle, 1);
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atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
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}
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static void __exit_idle(void)
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{
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if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
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return;
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atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
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}
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/* Called from interrupts to signify idle end */
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void exit_idle(void)
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{
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/* idle loop has pid 0 */
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if (current->pid)
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return;
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__exit_idle();
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}
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#endif
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/*
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* The idle thread. There's no useful work to be
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* done, so just try to conserve power and have a
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* low exit latency (ie sit in a loop waiting for
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* somebody to say that they'd like to reschedule)
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*/
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void cpu_idle(void)
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{
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/*
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* If we're the non-boot CPU, nothing set the stack canary up
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* for us. CPU0 already has it initialized but no harm in
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* doing it again. This is a good place for updating it, as
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* we wont ever return from this function (so the invalid
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* canaries already on the stack wont ever trigger).
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*/
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boot_init_stack_canary();
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current_thread_info()->status |= TS_POLLING;
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while (1) {
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tick_nohz_idle_enter();
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while (!need_resched()) {
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rmb();
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if (cpu_is_offline(smp_processor_id()))
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play_dead();
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/*
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* Idle routines should keep interrupts disabled
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* from here on, until they go to idle.
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* Otherwise, idle callbacks can misfire.
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*/
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local_touch_nmi();
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local_irq_disable();
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enter_idle();
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/* Don't trace irqs off for idle */
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stop_critical_timings();
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/* enter_idle() needs rcu for notifiers */
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rcu_idle_enter();
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if (cpuidle_idle_call())
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pm_idle();
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rcu_idle_exit();
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start_critical_timings();
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/* In many cases the interrupt that ended idle
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has already called exit_idle. But some idle
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loops can be woken up without interrupt. */
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__exit_idle();
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}
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tick_nohz_idle_exit();
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preempt_enable_no_resched();
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schedule();
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preempt_disable();
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}
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}
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/*
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* We use this if we don't have any better
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* idle routine..
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*/
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void default_idle(void)
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{
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if (hlt_use_halt()) {
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trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id());
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trace_cpu_idle_rcuidle(1, smp_processor_id());
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current_thread_info()->status &= ~TS_POLLING;
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/*
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* TS_POLLING-cleared state must be visible before we
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* test NEED_RESCHED:
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*/
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smp_mb();
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if (!need_resched())
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safe_halt(); /* enables interrupts racelessly */
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else
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local_irq_enable();
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current_thread_info()->status |= TS_POLLING;
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trace_power_end_rcuidle(smp_processor_id());
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trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
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} else {
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local_irq_enable();
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/* loop is done by the caller */
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cpu_relax();
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}
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}
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#ifdef CONFIG_APM_MODULE
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EXPORT_SYMBOL(default_idle);
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#endif
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bool set_pm_idle_to_default(void)
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{
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bool ret = !!pm_idle;
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pm_idle = default_idle;
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return ret;
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}
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void stop_this_cpu(void *dummy)
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{
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local_irq_disable();
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/*
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* Remove this CPU:
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*/
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set_cpu_online(smp_processor_id(), false);
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disable_local_APIC();
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for (;;) {
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if (hlt_works(smp_processor_id()))
|
|
halt();
|
|
}
|
|
}
|
|
|
|
static void do_nothing(void *unused)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* cpu_idle_wait - Used to ensure that all the CPUs discard old value of
|
|
* pm_idle and update to new pm_idle value. Required while changing pm_idle
|
|
* handler on SMP systems.
|
|
*
|
|
* Caller must have changed pm_idle to the new value before the call. Old
|
|
* pm_idle value will not be used by any CPU after the return of this function.
|
|
*/
|
|
void cpu_idle_wait(void)
|
|
{
|
|
smp_mb();
|
|
/* kick all the CPUs so that they exit out of pm_idle */
|
|
smp_call_function(do_nothing, NULL, 1);
|
|
}
|
|
EXPORT_SYMBOL_GPL(cpu_idle_wait);
|
|
|
|
/* Default MONITOR/MWAIT with no hints, used for default C1 state */
|
|
static void mwait_idle(void)
|
|
{
|
|
if (!need_resched()) {
|
|
trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id());
|
|
trace_cpu_idle_rcuidle(1, smp_processor_id());
|
|
if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
|
|
clflush((void *)¤t_thread_info()->flags);
|
|
|
|
__monitor((void *)¤t_thread_info()->flags, 0, 0);
|
|
smp_mb();
|
|
if (!need_resched())
|
|
__sti_mwait(0, 0);
|
|
else
|
|
local_irq_enable();
|
|
trace_power_end_rcuidle(smp_processor_id());
|
|
trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
|
|
} else
|
|
local_irq_enable();
|
|
}
|
|
|
|
/*
|
|
* On SMP it's slightly faster (but much more power-consuming!)
|
|
* to poll the ->work.need_resched flag instead of waiting for the
|
|
* cross-CPU IPI to arrive. Use this option with caution.
|
|
*/
|
|
static void poll_idle(void)
|
|
{
|
|
trace_power_start_rcuidle(POWER_CSTATE, 0, smp_processor_id());
|
|
trace_cpu_idle_rcuidle(0, smp_processor_id());
|
|
local_irq_enable();
|
|
while (!need_resched())
|
|
cpu_relax();
|
|
trace_power_end_rcuidle(smp_processor_id());
|
|
trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
|
|
}
|
|
|
|
/*
|
|
* mwait selection logic:
|
|
*
|
|
* It depends on the CPU. For AMD CPUs that support MWAIT this is
|
|
* wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
|
|
* then depend on a clock divisor and current Pstate of the core. If
|
|
* all cores of a processor are in halt state (C1) the processor can
|
|
* enter the C1E (C1 enhanced) state. If mwait is used this will never
|
|
* happen.
|
|
*
|
|
* idle=mwait overrides this decision and forces the usage of mwait.
|
|
*/
|
|
|
|
#define MWAIT_INFO 0x05
|
|
#define MWAIT_ECX_EXTENDED_INFO 0x01
|
|
#define MWAIT_EDX_C1 0xf0
|
|
|
|
int mwait_usable(const struct cpuinfo_x86 *c)
|
|
{
|
|
u32 eax, ebx, ecx, edx;
|
|
|
|
if (boot_option_idle_override == IDLE_FORCE_MWAIT)
|
|
return 1;
|
|
|
|
if (c->cpuid_level < MWAIT_INFO)
|
|
return 0;
|
|
|
|
cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
|
|
/* Check, whether EDX has extended info about MWAIT */
|
|
if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
|
|
return 1;
|
|
|
|
/*
|
|
* edx enumeratios MONITOR/MWAIT extensions. Check, whether
|
|
* C1 supports MWAIT
|
|
*/
|
|
return (edx & MWAIT_EDX_C1);
|
|
}
|
|
|
|
bool amd_e400_c1e_detected;
|
|
EXPORT_SYMBOL(amd_e400_c1e_detected);
|
|
|
|
static cpumask_var_t amd_e400_c1e_mask;
|
|
|
|
void amd_e400_remove_cpu(int cpu)
|
|
{
|
|
if (amd_e400_c1e_mask != NULL)
|
|
cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
|
|
}
|
|
|
|
/*
|
|
* AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
|
|
* pending message MSR. If we detect C1E, then we handle it the same
|
|
* way as C3 power states (local apic timer and TSC stop)
|
|
*/
|
|
static void amd_e400_idle(void)
|
|
{
|
|
if (need_resched())
|
|
return;
|
|
|
|
if (!amd_e400_c1e_detected) {
|
|
u32 lo, hi;
|
|
|
|
rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
|
|
|
|
if (lo & K8_INTP_C1E_ACTIVE_MASK) {
|
|
amd_e400_c1e_detected = true;
|
|
if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
|
|
mark_tsc_unstable("TSC halt in AMD C1E");
|
|
printk(KERN_INFO "System has AMD C1E enabled\n");
|
|
}
|
|
}
|
|
|
|
if (amd_e400_c1e_detected) {
|
|
int cpu = smp_processor_id();
|
|
|
|
if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
|
|
cpumask_set_cpu(cpu, amd_e400_c1e_mask);
|
|
/*
|
|
* Force broadcast so ACPI can not interfere.
|
|
*/
|
|
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
|
|
&cpu);
|
|
printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
|
|
cpu);
|
|
}
|
|
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
|
|
|
|
default_idle();
|
|
|
|
/*
|
|
* The switch back from broadcast mode needs to be
|
|
* called with interrupts disabled.
|
|
*/
|
|
local_irq_disable();
|
|
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
|
|
local_irq_enable();
|
|
} else
|
|
default_idle();
|
|
}
|
|
|
|
void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
|
|
{
|
|
#ifdef CONFIG_SMP
|
|
if (pm_idle == poll_idle && smp_num_siblings > 1) {
|
|
printk_once(KERN_WARNING "WARNING: polling idle and HT enabled,"
|
|
" performance may degrade.\n");
|
|
}
|
|
#endif
|
|
if (pm_idle)
|
|
return;
|
|
|
|
if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
|
|
/*
|
|
* One CPU supports mwait => All CPUs supports mwait
|
|
*/
|
|
printk(KERN_INFO "using mwait in idle threads.\n");
|
|
pm_idle = mwait_idle;
|
|
} else if (cpu_has_amd_erratum(amd_erratum_400)) {
|
|
/* E400: APIC timer interrupt does not wake up CPU from C1e */
|
|
printk(KERN_INFO "using AMD E400 aware idle routine\n");
|
|
pm_idle = amd_e400_idle;
|
|
} else
|
|
pm_idle = default_idle;
|
|
}
|
|
|
|
void __init init_amd_e400_c1e_mask(void)
|
|
{
|
|
/* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
|
|
if (pm_idle == amd_e400_idle)
|
|
zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
|
|
}
|
|
|
|
static int __init idle_setup(char *str)
|
|
{
|
|
if (!str)
|
|
return -EINVAL;
|
|
|
|
if (!strcmp(str, "poll")) {
|
|
printk("using polling idle threads.\n");
|
|
pm_idle = poll_idle;
|
|
boot_option_idle_override = IDLE_POLL;
|
|
} else if (!strcmp(str, "mwait")) {
|
|
boot_option_idle_override = IDLE_FORCE_MWAIT;
|
|
WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n");
|
|
} else if (!strcmp(str, "halt")) {
|
|
/*
|
|
* When the boot option of idle=halt is added, halt is
|
|
* forced to be used for CPU idle. In such case CPU C2/C3
|
|
* won't be used again.
|
|
* To continue to load the CPU idle driver, don't touch
|
|
* the boot_option_idle_override.
|
|
*/
|
|
pm_idle = default_idle;
|
|
boot_option_idle_override = IDLE_HALT;
|
|
} else if (!strcmp(str, "nomwait")) {
|
|
/*
|
|
* If the boot option of "idle=nomwait" is added,
|
|
* it means that mwait will be disabled for CPU C2/C3
|
|
* states. In such case it won't touch the variable
|
|
* of boot_option_idle_override.
|
|
*/
|
|
boot_option_idle_override = IDLE_NOMWAIT;
|
|
} else
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
early_param("idle", idle_setup);
|
|
|
|
unsigned long arch_align_stack(unsigned long sp)
|
|
{
|
|
if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
|
|
sp -= get_random_int() % 8192;
|
|
return sp & ~0xf;
|
|
}
|
|
|
|
unsigned long arch_randomize_brk(struct mm_struct *mm)
|
|
{
|
|
unsigned long range_end = mm->brk + 0x02000000;
|
|
return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
|
|
}
|
|
|