d6aef84a48
The babbage board has a DVI-I output which allows to output analog and digital signals simultaneously. This patch adds support for it to the devicetree. The DDC signals are not wired up on the board, so DRM will fall back on default VESA modes. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org>
283 lines
6.4 KiB
Text
283 lines
6.4 KiB
Text
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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/include/ "imx51.dtsi"
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/ {
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model = "Freescale i.MX51 Babbage Board";
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compatible = "fsl,imx51-babbage", "fsl,imx51";
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memory {
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reg = <0x90000000 0x20000000>;
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};
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soc {
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display@di0 {
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compatible = "fsl,imx-parallel-display";
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crtcs = <&ipu 0>;
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interface-pix-fmt = "rgb24";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu_disp1_1>;
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};
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display@di1 {
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compatible = "fsl,imx-parallel-display";
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crtcs = <&ipu 1>;
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interface-pix-fmt = "rgb565";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu_disp2_1>;
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};
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aips@70000000 { /* aips-1 */
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spba@70000000 {
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esdhc@70004000 { /* ESDHC1 */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1_1>;
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fsl,cd-controller;
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fsl,wp-controller;
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status = "okay";
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};
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esdhc@70008000 { /* ESDHC2 */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc2_1>;
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cd-gpios = <&gpio1 6 0>;
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wp-gpios = <&gpio1 5 0>;
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status = "okay";
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};
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uart3: serial@7000c000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3_1>;
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fsl,uart-has-rtscts;
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status = "okay";
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};
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ecspi@70010000 { /* ECSPI1 */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1_1>;
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
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status = "okay";
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pmic: mc13892@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mc13892";
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spi-max-frequency = <6000000>;
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reg = <0>;
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interrupt-parent = <&gpio1>;
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interrupts = <8 0x4>;
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regulators {
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sw1_reg: sw1 {
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <1375000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1850000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3_reg: sw3 {
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1850000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw4_reg: sw4 {
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1850000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vpll_reg: vpll {
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regulator-min-microvolt = <1050000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vdig_reg: vdig {
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regulator-min-microvolt = <1650000>;
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regulator-max-microvolt = <1650000>;
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regulator-boot-on;
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};
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vsd_reg: vsd {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3150000>;
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};
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vusb2_reg: vusb2 {
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regulator-min-microvolt = <2400000>;
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regulator-max-microvolt = <2775000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vvideo_reg: vvideo {
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regulator-min-microvolt = <2775000>;
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regulator-max-microvolt = <2775000>;
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};
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vaudio_reg: vaudio {
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regulator-min-microvolt = <2300000>;
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regulator-max-microvolt = <3000000>;
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};
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vcam_reg: vcam {
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <3000000>;
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};
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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};
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3150000>;
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regulator-always-on;
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};
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <2900000>;
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regulator-always-on;
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};
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};
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};
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flash: at45db321d@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
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spi-max-frequency = <25000000>;
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reg = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0x0 0x40000>;
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read-only;
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};
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partition@40000 {
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label = "Kernel";
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reg = <0x40000 0x3c0000>;
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};
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};
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};
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ssi2: ssi@70014000 {
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fsl,mode = "i2s-slave";
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status = "okay";
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};
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};
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iomuxc@73fa8000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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hog {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
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697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
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737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
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740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
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121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
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402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
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405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
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>;
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};
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};
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};
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uart1: serial@73fbc000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_1>;
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fsl,uart-has-rtscts;
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status = "okay";
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};
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uart2: serial@73fc0000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2_1>;
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status = "okay";
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};
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};
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aips@80000000 { /* aips-2 */
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i2c@83fc4000 { /* I2C2 */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2_1>;
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status = "okay";
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sgtl5000: codec@0a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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clock-frequency = <26000000>;
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VDDA-supply = <&vdig_reg>;
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VDDIO-supply = <&vvideo_reg>;
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};
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};
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audmux@83fd0000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux_1>;
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status = "okay";
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};
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ethernet@83fec000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec_1>;
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phy-mode = "mii";
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status = "okay";
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};
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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power {
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label = "Power Button";
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gpios = <&gpio2 21 0>;
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linux,code = <116>; /* KEY_POWER */
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gpio-key,wakeup;
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};
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};
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sound {
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compatible = "fsl,imx51-babbage-sgtl5000",
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"fsl,imx-audio-sgtl5000";
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model = "imx51-babbage-sgtl5000";
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ssi-controller = <&ssi2>;
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audio-codec = <&sgtl5000>;
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audio-routing =
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"MIC_IN", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"Headphone Jack", "HP_OUT";
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mux-int-port = <2>;
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mux-ext-port = <3>;
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};
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};
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