e81510e0c3
This avois a bug in modules trying to use the function. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
461 lines
13 KiB
C
461 lines
13 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* This code maintains the "home" for each page in the system.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/spinlock.h>
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#include <linux/list.h>
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#include <linux/bootmem.h>
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#include <linux/rmap.h>
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#include <linux/pagemap.h>
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#include <linux/mutex.h>
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#include <linux/interrupt.h>
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#include <linux/sysctl.h>
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#include <linux/pagevec.h>
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#include <linux/ptrace.h>
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#include <linux/timex.h>
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#include <linux/cache.h>
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#include <linux/smp.h>
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#include <linux/module.h>
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#include <asm/page.h>
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#include <asm/sections.h>
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#include <asm/tlbflush.h>
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#include <asm/pgalloc.h>
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#include <asm/homecache.h>
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#include <arch/sim.h>
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#include "migrate.h"
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#if CHIP_HAS_COHERENT_LOCAL_CACHE()
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/*
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* The noallocl2 option suppresses all use of the L2 cache to cache
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* locally from a remote home. There's no point in using it if we
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* don't have coherent local caching, though.
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*/
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static int __write_once noallocl2;
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static int __init set_noallocl2(char *str)
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{
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noallocl2 = 1;
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return 0;
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}
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early_param("noallocl2", set_noallocl2);
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#else
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#define noallocl2 0
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#endif
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/* Provide no-op versions of these routines to keep flush_remote() cleaner. */
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#define mark_caches_evicted_start() 0
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#define mark_caches_evicted_finish(mask, timestamp) do {} while (0)
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/*
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* Update the irq_stat for cpus that we are going to interrupt
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* with TLB or cache flushes. Also handle removing dataplane cpus
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* from the TLB flush set, and setting dataplane_tlb_state instead.
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*/
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static void hv_flush_update(const struct cpumask *cache_cpumask,
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struct cpumask *tlb_cpumask,
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unsigned long tlb_va, unsigned long tlb_length,
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HV_Remote_ASID *asids, int asidcount)
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{
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struct cpumask mask;
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int i, cpu;
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cpumask_clear(&mask);
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if (cache_cpumask)
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cpumask_or(&mask, &mask, cache_cpumask);
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if (tlb_cpumask && tlb_length) {
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cpumask_or(&mask, &mask, tlb_cpumask);
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}
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for (i = 0; i < asidcount; ++i)
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cpumask_set_cpu(asids[i].y * smp_width + asids[i].x, &mask);
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/*
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* Don't bother to update atomically; losing a count
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* here is not that critical.
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*/
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for_each_cpu(cpu, &mask)
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++per_cpu(irq_stat, cpu).irq_hv_flush_count;
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}
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/*
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* This wrapper function around hv_flush_remote() does several things:
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*
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* - Provides a return value error-checking panic path, since
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* there's never any good reason for hv_flush_remote() to fail.
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* - Accepts a 32-bit PFN rather than a 64-bit PA, which generally
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* is the type that Linux wants to pass around anyway.
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* - Centralizes the mark_caches_evicted() handling.
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* - Canonicalizes that lengths of zero make cpumasks NULL.
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* - Handles deferring TLB flushes for dataplane tiles.
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* - Tracks remote interrupts in the per-cpu irq_cpustat_t.
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*
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* Note that we have to wait until the cache flush completes before
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* updating the per-cpu last_cache_flush word, since otherwise another
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* concurrent flush can race, conclude the flush has already
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* completed, and start to use the page while it's still dirty
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* remotely (running concurrently with the actual evict, presumably).
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*/
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void flush_remote(unsigned long cache_pfn, unsigned long cache_control,
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const struct cpumask *cache_cpumask_orig,
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HV_VirtAddr tlb_va, unsigned long tlb_length,
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unsigned long tlb_pgsize,
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const struct cpumask *tlb_cpumask_orig,
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HV_Remote_ASID *asids, int asidcount)
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{
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int rc;
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int timestamp = 0; /* happy compiler */
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struct cpumask cache_cpumask_copy, tlb_cpumask_copy;
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struct cpumask *cache_cpumask, *tlb_cpumask;
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HV_PhysAddr cache_pa;
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char cache_buf[NR_CPUS*5], tlb_buf[NR_CPUS*5];
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mb(); /* provided just to simplify "magic hypervisor" mode */
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/*
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* Canonicalize and copy the cpumasks.
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*/
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if (cache_cpumask_orig && cache_control) {
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cpumask_copy(&cache_cpumask_copy, cache_cpumask_orig);
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cache_cpumask = &cache_cpumask_copy;
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} else {
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cpumask_clear(&cache_cpumask_copy);
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cache_cpumask = NULL;
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}
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if (cache_cpumask == NULL)
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cache_control = 0;
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if (tlb_cpumask_orig && tlb_length) {
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cpumask_copy(&tlb_cpumask_copy, tlb_cpumask_orig);
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tlb_cpumask = &tlb_cpumask_copy;
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} else {
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cpumask_clear(&tlb_cpumask_copy);
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tlb_cpumask = NULL;
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}
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hv_flush_update(cache_cpumask, tlb_cpumask, tlb_va, tlb_length,
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asids, asidcount);
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cache_pa = (HV_PhysAddr)cache_pfn << PAGE_SHIFT;
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if (cache_control & HV_FLUSH_EVICT_L2)
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timestamp = mark_caches_evicted_start();
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rc = hv_flush_remote(cache_pa, cache_control,
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cpumask_bits(cache_cpumask),
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tlb_va, tlb_length, tlb_pgsize,
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cpumask_bits(tlb_cpumask),
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asids, asidcount);
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if (cache_control & HV_FLUSH_EVICT_L2)
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mark_caches_evicted_finish(cache_cpumask, timestamp);
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if (rc == 0)
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return;
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cpumask_scnprintf(cache_buf, sizeof(cache_buf), &cache_cpumask_copy);
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cpumask_scnprintf(tlb_buf, sizeof(tlb_buf), &tlb_cpumask_copy);
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pr_err("hv_flush_remote(%#llx, %#lx, %p [%s],"
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" %#lx, %#lx, %#lx, %p [%s], %p, %d) = %d\n",
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cache_pa, cache_control, cache_cpumask, cache_buf,
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(unsigned long)tlb_va, tlb_length, tlb_pgsize,
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tlb_cpumask, tlb_buf,
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asids, asidcount, rc);
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panic("Unsafe to continue.");
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}
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void flush_remote_page(struct page *page, int order)
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{
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int i, pages = (1 << order);
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for (i = 0; i < pages; ++i, ++page) {
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void *p = kmap_atomic(page);
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int hfh = 0;
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int home = page_home(page);
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#if CHIP_HAS_CBOX_HOME_MAP()
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if (home == PAGE_HOME_HASH)
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hfh = 1;
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else
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#endif
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BUG_ON(home < 0 || home >= NR_CPUS);
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finv_buffer_remote(p, PAGE_SIZE, hfh);
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kunmap_atomic(p);
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}
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}
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void homecache_evict(const struct cpumask *mask)
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{
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flush_remote(0, HV_FLUSH_EVICT_L2, mask, 0, 0, 0, NULL, NULL, 0);
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}
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/*
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* Return a mask of the cpus whose caches currently own these pages.
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* The return value is whether the pages are all coherently cached
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* (i.e. none are immutable, incoherent, or uncached).
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*/
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static int homecache_mask(struct page *page, int pages,
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struct cpumask *home_mask)
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{
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int i;
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int cached_coherently = 1;
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cpumask_clear(home_mask);
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for (i = 0; i < pages; ++i) {
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int home = page_home(&page[i]);
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if (home == PAGE_HOME_IMMUTABLE ||
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home == PAGE_HOME_INCOHERENT) {
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cpumask_copy(home_mask, cpu_possible_mask);
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return 0;
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}
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#if CHIP_HAS_CBOX_HOME_MAP()
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if (home == PAGE_HOME_HASH) {
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cpumask_or(home_mask, home_mask, &hash_for_home_map);
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continue;
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}
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#endif
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if (home == PAGE_HOME_UNCACHED) {
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cached_coherently = 0;
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continue;
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}
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BUG_ON(home < 0 || home >= NR_CPUS);
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cpumask_set_cpu(home, home_mask);
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}
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return cached_coherently;
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}
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/*
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* Return the passed length, or zero if it's long enough that we
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* believe we should evict the whole L2 cache.
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*/
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static unsigned long cache_flush_length(unsigned long length)
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{
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return (length >= CHIP_L2_CACHE_SIZE()) ? HV_FLUSH_EVICT_L2 : length;
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}
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/* Flush a page out of whatever cache(s) it is in. */
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void homecache_flush_cache(struct page *page, int order)
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{
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int pages = 1 << order;
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int length = cache_flush_length(pages * PAGE_SIZE);
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unsigned long pfn = page_to_pfn(page);
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struct cpumask home_mask;
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homecache_mask(page, pages, &home_mask);
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flush_remote(pfn, length, &home_mask, 0, 0, 0, NULL, NULL, 0);
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sim_validate_lines_evicted(PFN_PHYS(pfn), pages * PAGE_SIZE);
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}
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/* Report the home corresponding to a given PTE. */
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static int pte_to_home(pte_t pte)
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{
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if (hv_pte_get_nc(pte))
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return PAGE_HOME_IMMUTABLE;
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switch (hv_pte_get_mode(pte)) {
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case HV_PTE_MODE_CACHE_TILE_L3:
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return get_remote_cache_cpu(pte);
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case HV_PTE_MODE_CACHE_NO_L3:
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return PAGE_HOME_INCOHERENT;
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case HV_PTE_MODE_UNCACHED:
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return PAGE_HOME_UNCACHED;
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#if CHIP_HAS_CBOX_HOME_MAP()
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case HV_PTE_MODE_CACHE_HASH_L3:
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return PAGE_HOME_HASH;
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#endif
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}
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panic("Bad PTE %#llx\n", pte.val);
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}
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/* Update the home of a PTE if necessary (can also be used for a pgprot_t). */
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pte_t pte_set_home(pte_t pte, int home)
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{
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/* Check for non-linear file mapping "PTEs" and pass them through. */
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if (pte_file(pte))
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return pte;
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#if CHIP_HAS_MMIO()
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/* Check for MMIO mappings and pass them through. */
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if (hv_pte_get_mode(pte) == HV_PTE_MODE_MMIO)
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return pte;
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#endif
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/*
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* Only immutable pages get NC mappings. If we have a
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* non-coherent PTE, but the underlying page is not
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* immutable, it's likely the result of a forced
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* caching setting running up against ptrace setting
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* the page to be writable underneath. In this case,
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* just keep the PTE coherent.
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*/
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if (hv_pte_get_nc(pte) && home != PAGE_HOME_IMMUTABLE) {
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pte = hv_pte_clear_nc(pte);
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pr_err("non-immutable page incoherently referenced: %#llx\n",
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pte.val);
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}
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switch (home) {
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case PAGE_HOME_UNCACHED:
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pte = hv_pte_set_mode(pte, HV_PTE_MODE_UNCACHED);
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break;
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case PAGE_HOME_INCOHERENT:
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pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_NO_L3);
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break;
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case PAGE_HOME_IMMUTABLE:
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/*
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* We could home this page anywhere, since it's immutable,
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* but by default just home it to follow "hash_default".
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*/
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BUG_ON(hv_pte_get_writable(pte));
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if (pte_get_forcecache(pte)) {
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/* Upgrade "force any cpu" to "No L3" for immutable. */
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if (hv_pte_get_mode(pte) == HV_PTE_MODE_CACHE_TILE_L3
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&& pte_get_anyhome(pte)) {
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pte = hv_pte_set_mode(pte,
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HV_PTE_MODE_CACHE_NO_L3);
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}
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} else
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#if CHIP_HAS_CBOX_HOME_MAP()
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if (hash_default)
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pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_HASH_L3);
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else
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#endif
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pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_NO_L3);
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pte = hv_pte_set_nc(pte);
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break;
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#if CHIP_HAS_CBOX_HOME_MAP()
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case PAGE_HOME_HASH:
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pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_HASH_L3);
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break;
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#endif
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default:
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BUG_ON(home < 0 || home >= NR_CPUS ||
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!cpu_is_valid_lotar(home));
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pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_TILE_L3);
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pte = set_remote_cache_cpu(pte, home);
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break;
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}
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#if CHIP_HAS_NC_AND_NOALLOC_BITS()
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if (noallocl2)
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pte = hv_pte_set_no_alloc_l2(pte);
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/* Simplify "no local and no l3" to "uncached" */
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if (hv_pte_get_no_alloc_l2(pte) && hv_pte_get_no_alloc_l1(pte) &&
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hv_pte_get_mode(pte) == HV_PTE_MODE_CACHE_NO_L3) {
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pte = hv_pte_set_mode(pte, HV_PTE_MODE_UNCACHED);
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}
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#endif
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/* Checking this case here gives a better panic than from the hv. */
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BUG_ON(hv_pte_get_mode(pte) == 0);
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return pte;
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}
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EXPORT_SYMBOL(pte_set_home);
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/*
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* The routines in this section are the "static" versions of the normal
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* dynamic homecaching routines; they just set the home cache
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* of a kernel page once, and require a full-chip cache/TLB flush,
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* so they're not suitable for anything but infrequent use.
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*/
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#if CHIP_HAS_CBOX_HOME_MAP()
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static inline int initial_page_home(void) { return PAGE_HOME_HASH; }
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#else
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static inline int initial_page_home(void) { return 0; }
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#endif
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int page_home(struct page *page)
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{
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if (PageHighMem(page)) {
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return initial_page_home();
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} else {
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unsigned long kva = (unsigned long)page_address(page);
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return pte_to_home(*virt_to_pte(NULL, kva));
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}
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}
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EXPORT_SYMBOL(page_home);
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void homecache_change_page_home(struct page *page, int order, int home)
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{
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int i, pages = (1 << order);
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unsigned long kva;
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BUG_ON(PageHighMem(page));
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BUG_ON(page_count(page) > 1);
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BUG_ON(page_mapcount(page) != 0);
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kva = (unsigned long) page_address(page);
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flush_remote(0, HV_FLUSH_EVICT_L2, &cpu_cacheable_map,
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kva, pages * PAGE_SIZE, PAGE_SIZE, cpu_online_mask,
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NULL, 0);
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for (i = 0; i < pages; ++i, kva += PAGE_SIZE) {
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pte_t *ptep = virt_to_pte(NULL, kva);
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pte_t pteval = *ptep;
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BUG_ON(!pte_present(pteval) || pte_huge(pteval));
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__set_pte(ptep, pte_set_home(pteval, home));
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}
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}
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struct page *homecache_alloc_pages(gfp_t gfp_mask,
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unsigned int order, int home)
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{
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struct page *page;
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BUG_ON(gfp_mask & __GFP_HIGHMEM); /* must be lowmem */
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page = alloc_pages(gfp_mask, order);
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if (page)
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homecache_change_page_home(page, order, home);
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return page;
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}
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EXPORT_SYMBOL(homecache_alloc_pages);
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struct page *homecache_alloc_pages_node(int nid, gfp_t gfp_mask,
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unsigned int order, int home)
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{
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struct page *page;
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BUG_ON(gfp_mask & __GFP_HIGHMEM); /* must be lowmem */
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page = alloc_pages_node(nid, gfp_mask, order);
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if (page)
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homecache_change_page_home(page, order, home);
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return page;
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}
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void homecache_free_pages(unsigned long addr, unsigned int order)
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{
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struct page *page;
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if (addr == 0)
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return;
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VM_BUG_ON(!virt_addr_valid((void *)addr));
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page = virt_to_page((void *)addr);
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if (put_page_testzero(page)) {
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homecache_change_page_home(page, order, initial_page_home());
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if (order == 0) {
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free_hot_cold_page(page, 0);
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} else {
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init_page_count(page);
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__free_pages(page, order);
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}
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}
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}
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