8c0236fc46
Clock framework for SPEAr is based upon clkdev framework for ARM Reviewed-by: Linus Walleij <linux.walleij@stericsson.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
126 lines
3.2 KiB
C
126 lines
3.2 KiB
C
/*
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* arch/arm/plat-spear/include/plat/clock.h
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*
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* Clock framework definitions for SPEAr platform
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __PLAT_CLOCK_H
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#define __PLAT_CLOCK_H
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#include <linux/list.h>
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#include <asm/clkdev.h>
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#include <linux/types.h>
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/* clk structure flags */
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#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */
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#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */
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/**
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* struct clkops - clock operations
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* @enable: pointer to clock enable function
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* @disable: pointer to clock disable function
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*/
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struct clkops {
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int (*enable) (struct clk *);
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void (*disable) (struct clk *);
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};
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/**
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* struct pclk_info - parents info
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* @pclk: pointer to parent clk
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* @pclk_mask: value to be written for selecting this parent
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* @scalable: Is parent scalable (1 - YES, 0 - NO)
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*/
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struct pclk_info {
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struct clk *pclk;
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u8 pclk_mask;
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u8 scalable;
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};
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/**
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* struct pclk_sel - parents selection configuration
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* @pclk_info: pointer to array of parent clock info
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* @pclk_count: number of parents
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* @pclk_sel_reg: register for selecting a parent
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* @pclk_sel_mask: mask for selecting parent (can be used to clear bits also)
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*/
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struct pclk_sel {
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struct pclk_info *pclk_info;
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u8 pclk_count;
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unsigned int *pclk_sel_reg;
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unsigned int pclk_sel_mask;
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};
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/**
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* struct clk - clock structure
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* @usage_count: num of users who enabled this clock
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* @flags: flags for clock properties
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* @rate: programmed clock rate in Hz
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* @en_reg: clk enable/disable reg
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* @en_reg_bit: clk enable/disable bit
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* @ops: clk enable/disable ops - generic_clkops selected if NULL
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* @recalc: pointer to clock rate recalculate function
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* @pclk: current parent clk
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* @pclk_sel: pointer to parent selection structure
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* @pclk_sel_shift: register shift for selecting parent of this clock
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* @children: list for childrens or this clock
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* @sibling: node for list of clocks having same parents
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* @private_data: clock specific private data
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*/
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struct clk {
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unsigned int usage_count;
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unsigned int flags;
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unsigned long rate;
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unsigned int *en_reg;
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u8 en_reg_bit;
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const struct clkops *ops;
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void (*recalc) (struct clk *);
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struct clk *pclk;
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struct pclk_sel *pclk_sel;
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unsigned int pclk_sel_shift;
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struct list_head children;
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struct list_head sibling;
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void *private_data;
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};
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/* pll configuration structure */
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struct pll_clk_config {
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unsigned int *mode_reg;
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unsigned int *cfg_reg;
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};
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/* ahb and apb bus configuration structure */
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struct bus_clk_config {
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unsigned int *reg;
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unsigned int mask;
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unsigned int shift;
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};
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/*
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* Aux clk configuration structure: applicable to GPT, UART and FIRDA
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*/
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struct aux_clk_config {
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unsigned int *synth_reg;
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};
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/* platform specific clock functions */
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void clk_register(struct clk_lookup *cl);
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void recalc_root_clocks(void);
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/* clock recalc functions */
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void follow_parent(struct clk *clk);
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void pll1_clk_recalc(struct clk *clk);
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void bus_clk_recalc(struct clk *clk);
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void gpt_clk_recalc(struct clk *clk);
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void aux_clk_recalc(struct clk *clk);
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#endif /* __PLAT_CLOCK_H */
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