30aacebed0
This patch adds workaround for PPC 440GX erratum 440_43. According to this erratum spurious MachineChecks (caused by L1 cache parity) can happen during DataTLB miss processing. We disable L1 cache parity checking for 440GX rev.C and rev.F Signed-off-by: Eugene Surovegin <ebs@ebshome.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
59 lines
1.6 KiB
C
59 lines
1.6 KiB
C
/*
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* PPC440GX system library
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*
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003, 2004 Zultys Technologies
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifdef __KERNEL__
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#ifndef __PPC_SYSLIB_IBM440GX_COMMON_H
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#define __PPC_SYSLIB_IBM440GX_COMMON_H
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#ifndef __ASSEMBLY__
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/seq_file.h>
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#include <syslib/ibm44x_common.h>
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/*
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* Please, refer to the Figure 14.1 in 440GX user manual
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*
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* if internal UART clock is used, ser_clk is ignored
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*/
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void ibm440gx_get_clocks(struct ibm44x_clocks*, unsigned int sys_clk,
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unsigned int ser_clk) __init;
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/* common 440GX platform init */
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void ibm440gx_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7) __init;
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/* Enable L2 cache */
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void ibm440gx_l2c_enable(void) __init;
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/* Disable L2 cache */
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void ibm440gx_l2c_disable(void) __init;
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/* Enable/disable L2 cache for a particular chip revision */
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void ibm440gx_l2c_setup(struct ibm44x_clocks*) __init;
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/* Get Ethernet Group */
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int ibm440gx_get_eth_grp(void) __init;
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/* Set Ethernet Group */
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void ibm440gx_set_eth_grp(int group) __init;
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/* Enable TAH devices */
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void ibm440gx_tah_enable(void) __init;
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/* Add L2C info to /proc/cpuinfo */
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int ibm440gx_show_cpuinfo(struct seq_file*);
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#endif /* __ASSEMBLY__ */
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#endif /* __PPC_SYSLIB_IBM440GX_COMMON_H */
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#endif /* __KERNEL__ */
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