fbb18a277a
The amba-pl010 hardware does not provide RTS and DTR control lines; it is expected that these will be implemented using GPIO. Allow platforms to supply a function to implement manipulation of modem control lines. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
321 lines
7.1 KiB
C
321 lines
7.1 KiB
C
/*
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* linux/arch/arm/mach-integrator/core.c
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*
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* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/termios.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/serial.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/arch/cm.h>
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#include <asm/system.h>
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#include <asm/leds.h>
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#include <asm/mach/time.h>
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#include "common.h"
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static struct amba_pl010_data integrator_uart_data;
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static struct amba_device rtc_device = {
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.dev = {
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.bus_id = "mb:15",
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},
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.res = {
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.start = INTEGRATOR_RTC_BASE,
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.end = INTEGRATOR_RTC_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_RTCINT, NO_IRQ },
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.periphid = 0x00041030,
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};
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static struct amba_device uart0_device = {
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.dev = {
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.bus_id = "mb:16",
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.platform_data = &integrator_uart_data,
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},
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.res = {
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.start = INTEGRATOR_UART0_BASE,
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.end = INTEGRATOR_UART0_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_UARTINT0, NO_IRQ },
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.periphid = 0x0041010,
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};
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static struct amba_device uart1_device = {
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.dev = {
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.bus_id = "mb:17",
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.platform_data = &integrator_uart_data,
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},
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.res = {
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.start = INTEGRATOR_UART1_BASE,
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.end = INTEGRATOR_UART1_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_UARTINT1, NO_IRQ },
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.periphid = 0x0041010,
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};
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static struct amba_device kmi0_device = {
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.dev = {
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.bus_id = "mb:18",
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},
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.res = {
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.start = KMI0_BASE,
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.end = KMI0_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_KMIINT0, NO_IRQ },
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.periphid = 0x00041050,
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};
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static struct amba_device kmi1_device = {
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.dev = {
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.bus_id = "mb:19",
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},
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.res = {
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.start = KMI1_BASE,
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.end = KMI1_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_KMIINT1, NO_IRQ },
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.periphid = 0x00041050,
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};
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static struct amba_device *amba_devs[] __initdata = {
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&rtc_device,
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&uart0_device,
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&uart1_device,
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&kmi0_device,
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&kmi1_device,
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};
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static int __init integrator_init(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
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struct amba_device *d = amba_devs[i];
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amba_device_register(d, &iomem_resource);
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}
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return 0;
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}
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arch_initcall(integrator_init);
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/*
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* On the Integrator platform, the port RTS and DTR are provided by
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* bits in the following SC_CTRLS register bits:
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* RTS DTR
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* UART0 7 6
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* UART1 5 4
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*/
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#define SC_CTRLC (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET)
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#define SC_CTRLS (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET)
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static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
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{
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unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
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if (dev == &uart0_device) {
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rts_mask = 1 << 4;
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dtr_mask = 1 << 5;
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} else {
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rts_mask = 1 << 6;
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dtr_mask = 1 << 7;
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}
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if (mctrl & TIOCM_RTS)
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ctrlc |= rts_mask;
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else
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ctrls |= rts_mask;
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if (mctrl & TIOCM_DTR)
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ctrlc |= dtr_mask;
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else
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ctrls |= dtr_mask;
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__raw_writel(ctrls, SC_CTRLS);
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__raw_writel(ctrlc, SC_CTRLC);
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}
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static struct amba_pl010_data integrator_uart_data = {
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.set_mctrl = integrator_uart_set_mctrl,
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};
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#define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_CTRL_OFFSET
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static DEFINE_SPINLOCK(cm_lock);
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/**
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* cm_control - update the CM_CTRL register.
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* @mask: bits to change
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* @set: bits to set
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*/
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void cm_control(u32 mask, u32 set)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&cm_lock, flags);
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val = readl(CM_CTRL) & ~mask;
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writel(val | set, CM_CTRL);
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spin_unlock_irqrestore(&cm_lock, flags);
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}
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EXPORT_SYMBOL(cm_control);
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/*
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* Where is the timer (VA)?
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*/
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#define TIMER0_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000000)
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#define TIMER1_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000100)
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#define TIMER2_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000200)
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#define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
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/*
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* How long is the timer interval?
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*/
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#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
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#if TIMER_INTERVAL >= 0x100000
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#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
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#elif TIMER_INTERVAL >= 0x10000
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#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
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#else
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#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
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#endif
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static unsigned long timer_reload;
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/*
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* Returns number of ms since last clock interrupt. Note that interrupts
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* will have been disabled by do_gettimeoffset()
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*/
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unsigned long integrator_gettimeoffset(void)
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{
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unsigned long ticks1, ticks2, status;
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/*
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* Get the current number of ticks. Note that there is a race
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* condition between us reading the timer and checking for
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* an interrupt. We get around this by ensuring that the
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* counter has not reloaded between our two reads.
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*/
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ticks2 = readl(TIMER1_VA_BASE + TIMER_VALUE) & 0xffff;
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do {
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ticks1 = ticks2;
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status = __raw_readl(VA_IC_BASE + IRQ_RAW_STATUS);
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ticks2 = readl(TIMER1_VA_BASE + TIMER_VALUE) & 0xffff;
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} while (ticks2 > ticks1);
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/*
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* Number of ticks since last interrupt.
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*/
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ticks1 = timer_reload - ticks2;
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/*
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* Interrupt pending? If so, we've reloaded once already.
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*/
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if (status & (1 << IRQ_TIMERINT1))
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ticks1 += timer_reload;
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/*
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* Convert the ticks to usecs
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*/
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return TICKS2USECS(ticks1);
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}
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t
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integrator_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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write_seqlock(&xtime_lock);
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/*
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* clear the interrupt
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*/
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writel(1, TIMER1_VA_BASE + TIMER_INTCLR);
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/*
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* the clock tick routines are only processed on the
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* primary CPU
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*/
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if (hard_smp_processor_id() == 0) {
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timer_tick(regs);
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#ifdef CONFIG_SMP
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smp_send_timer();
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#endif
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}
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#ifdef CONFIG_SMP
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/*
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* this is the ARM equivalent of the APIC timer interrupt
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*/
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update_process_times(user_mode(regs));
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#endif /* CONFIG_SMP */
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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static struct irqaction integrator_timer_irq = {
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.name = "Integrator Timer Tick",
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.flags = SA_INTERRUPT | SA_TIMER,
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.handler = integrator_timer_interrupt,
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};
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/*
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* Set up timer interrupt, and return the current time in seconds.
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*/
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void __init integrator_time_init(unsigned long reload, unsigned int ctrl)
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{
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unsigned int timer_ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
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timer_reload = reload;
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timer_ctrl |= ctrl;
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if (timer_reload > 0x100000) {
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timer_reload >>= 8;
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timer_ctrl |= TIMER_CTRL_DIV256;
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} else if (timer_reload > 0x010000) {
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timer_reload >>= 4;
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timer_ctrl |= TIMER_CTRL_DIV16;
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}
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/*
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* Initialise to a known state (all timers off)
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*/
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writel(0, TIMER0_VA_BASE + TIMER_CTRL);
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writel(0, TIMER1_VA_BASE + TIMER_CTRL);
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writel(0, TIMER2_VA_BASE + TIMER_CTRL);
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writel(timer_reload, TIMER1_VA_BASE + TIMER_LOAD);
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writel(timer_reload, TIMER1_VA_BASE + TIMER_VALUE);
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writel(timer_ctrl, TIMER1_VA_BASE + TIMER_CTRL);
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/*
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* Make irqs happen for the system timer
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*/
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setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
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}
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