18aecc2b64
This support was partially present in the existing code (look for "__tilegx__" ifdefs) but with this change you can build a working kernel using the TILE-Gx toolchain and ARCH=tilegx. Most of these files are new, generally adding a foo_64.c file where previously there was just a foo_32.c file. The ARCH=tilegx directive redirects to arch/tile, not arch/tilegx, using the existing SRCARCH mechanism in the top-level Makefile. Changes to existing files: - <asm/bitops.h> and <asm/bitops_32.h> changed to factor the include of <asm-generic/bitops/non-atomic.h> in the common header. - <asm/compat.h> and arch/tile/kernel/compat.c changed to remove the "const" markers I had put on compat_sys_execve() when trying to match some recent similar changes to the non-compat execve. It turns out the compat version wasn't "upgraded" to use const. - <asm/opcode-tile_64.h> and <asm/opcode_constants_64.h> were previously included accidentally, with the 32-bit contents. Now they have the proper 64-bit contents. Finally, I had to hack the existing hacky drivers/input/input-compat.h to add yet another "#ifdef" for INPUT_COMPAT_TEST (same as x86_64). Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> [drivers/input]
131 lines
4.2 KiB
C
131 lines
4.2 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_BITOPS_32_H
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#define _ASM_TILE_BITOPS_32_H
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#include <linux/compiler.h>
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#include <asm/atomic.h>
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#include <asm/system.h>
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/* Tile-specific routines to support <asm/bitops.h>. */
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unsigned long _atomic_or(volatile unsigned long *p, unsigned long mask);
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unsigned long _atomic_andn(volatile unsigned long *p, unsigned long mask);
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unsigned long _atomic_xor(volatile unsigned long *p, unsigned long mask);
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered.
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* See __set_bit() if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void set_bit(unsigned nr, volatile unsigned long *addr)
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{
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_atomic_or(addr + BIT_WORD(nr), BIT_MASK(nr));
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}
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered.
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* See __clear_bit() if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*
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* clear_bit() may not contain a memory barrier, so if it is used for
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* locking purposes, you should call smp_mb__before_clear_bit() and/or
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* smp_mb__after_clear_bit() to ensure changes are visible on other cpus.
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*/
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static inline void clear_bit(unsigned nr, volatile unsigned long *addr)
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{
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_atomic_andn(addr + BIT_WORD(nr), BIT_MASK(nr));
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}
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/**
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* change_bit - Toggle a bit in memory
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* @nr: Bit to change
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered.
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* See __change_bit() if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void change_bit(unsigned nr, volatile unsigned long *addr)
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{
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_atomic_xor(addr + BIT_WORD(nr), BIT_MASK(nr));
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}
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/**
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_set_bit(unsigned nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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addr += BIT_WORD(nr);
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smp_mb(); /* barrier for proper semantics */
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return (_atomic_or(addr, mask) & mask) != 0;
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_clear_bit(unsigned nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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addr += BIT_WORD(nr);
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smp_mb(); /* barrier for proper semantics */
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return (_atomic_andn(addr, mask) & mask) != 0;
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}
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/**
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* test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to change
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_change_bit(unsigned nr,
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volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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addr += BIT_WORD(nr);
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smp_mb(); /* barrier for proper semantics */
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return (_atomic_xor(addr, mask) & mask) != 0;
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}
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/* See discussion at smp_mb__before_atomic_dec() in <asm/atomic_32.h>. */
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#define smp_mb__before_clear_bit() smp_mb()
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#define smp_mb__after_clear_bit() do {} while (0)
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#include <asm-generic/bitops/ext2-atomic.h>
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#endif /* _ASM_TILE_BITOPS_32_H */
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