827634adde
We will need it for atomic.h, so move it from the ad-hoc tools/perf/ place to a tools/ subset of the kernel arch/ hierarchy. Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Borislav Petkov <bp@suse.de> Cc: David Ahern <dsahern@gmail.com> Cc: Don Zickus <dzickus@redhat.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Stephane Eranian <eranian@google.com> Link: http://lkml.kernel.org/n/tip-6xqb97k782wqp1r3v6jqayki@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
32 lines
1 KiB
C
32 lines
1 KiB
C
/*
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* Copied from the kernel sources:
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*
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* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
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* Copyright (C) 2002 Paul Mundt
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*/
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#ifndef __TOOLS_LINUX_ASM_SH_BARRIER_H
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#define __TOOLS_LINUX_ASM_SH_BARRIER_H
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/*
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* A brief note on ctrl_barrier(), the control register write barrier.
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*
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* Legacy SH cores typically require a sequence of 8 nops after
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* modification of a control register in order for the changes to take
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* effect. On newer cores (like the sh4a and sh5) this is accomplished
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* with icbi.
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*
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* Also note that on sh4a in the icbi case we can forego a synco for the
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* write barrier, as it's not necessary for control registers.
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*
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* Historically we have only done this type of barrier for the MMUCR, but
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* it's also necessary for the CCR, so we make it generic here instead.
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*/
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#if defined(__SH4A__) || defined(__SH5__)
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#define mb() __asm__ __volatile__ ("synco": : :"memory")
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#define rmb() mb()
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#define wmb() mb()
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#endif
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#include <asm-generic/barrier.h>
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#endif /* __TOOLS_LINUX_ASM_SH_BARRIER_H */
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