b9f2d172f2
GPIO register and configuration definitions for GPIO banks D, E and F. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
71 lines
2.3 KiB
C
71 lines
2.3 KiB
C
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* GPIO Bank F register and configuration definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define S3C64XX_GPFCON (S3C64XX_GPF_BASE + 0x00)
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#define S3C64XX_GPFDAT (S3C64XX_GPF_BASE + 0x04)
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#define S3C64XX_GPFPUD (S3C64XX_GPF_BASE + 0x08)
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#define S3C64XX_GPFCONSLP (S3C64XX_GPF_BASE + 0x0c)
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#define S3C64XX_GPFPUDSLP (S3C64XX_GPF_BASE + 0x10)
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#define S3C64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
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#define S3C64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2))
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#define S3C64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
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#define S3C64XX_GPF0_CAMIF_CLK (0x02 << 0)
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#define S3C64XX_GPF0_EINT_G4_0 (0x03 << 0)
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#define S3C64XX_GPF1_CAMIF_HREF (0x02 << 2)
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#define S3C64XX_GPF1_EINT_G4_1 (0x03 << 2)
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#define S3C64XX_GPF2_CAMIF_PCLK (0x02 << 4)
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#define S3C64XX_GPF2_EINT_G4_2 (0x03 << 4)
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#define S3C64XX_GPF3_CAMIF_nRST (0x02 << 6)
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#define S3C64XX_GPF3_EINT_G4_3 (0x03 << 6)
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#define S3C64XX_GPF4_CAMIF_VSYNC (0x02 << 8)
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#define S3C64XX_GPF4_EINT_G4_4 (0x03 << 8)
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#define S3C64XX_GPF5_CAMIF_YDATA0 (0x02 << 10)
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#define S3C64XX_GPF5_EINT_G4_5 (0x03 << 10)
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#define S3C64XX_GPF6_CAMIF_YDATA1 (0x02 << 12)
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#define S3C64XX_GPF6_EINT_G4_6 (0x03 << 12)
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#define S3C64XX_GPF7_CAMIF_YDATA2 (0x02 << 14)
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#define S3C64XX_GPF7_EINT_G4_7 (0x03 << 14)
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#define S3C64XX_GPF8_CAMIF_YDATA3 (0x02 << 16)
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#define S3C64XX_GPF8_EINT_G4_8 (0x03 << 16)
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#define S3C64XX_GPF9_CAMIF_YDATA4 (0x02 << 18)
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#define S3C64XX_GPF9_EINT_G4_9 (0x03 << 18)
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#define S3C64XX_GPF10_CAMIF_YDATA5 (0x02 << 20)
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#define S3C64XX_GPF10_EINT_G4_10 (0x03 << 20)
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#define S3C64XX_GPF11_CAMIF_YDATA6 (0x02 << 22)
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#define S3C64XX_GPF11_EINT_G4_11 (0x03 << 22)
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#define S3C64XX_GPF12_CAMIF_YDATA7 (0x02 << 24)
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#define S3C64XX_GPF12_EINT_G4_12 (0x03 << 24)
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#define S3C64XX_GPF13_PWM_ECLK (0x02 << 26)
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#define S3C64XX_GPF13_EINT_G4_13 (0x03 << 26)
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#define S3C64XX_GPF14_PWM_TOUT0 (0x02 << 28)
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#define S3C64XX_GPF14_CLKOUT0 (0x03 << 28)
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#define S3C64XX_GPF15_PWM_TOUT1 (0x02 << 30)
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