afb7d3cd80
Instead of hardcoding the hci_io_ds configuration that we write to the SDIO_IO_DS top registed, read it from the default configuration so that it's easier to change for different platforms. Reported-by: Ido Yariv <ido@wizery.com> Signed-off-by: Luciano Coelho <coelho@ti.com>
129 lines
3.7 KiB
C
129 lines
3.7 KiB
C
/*
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* This file is part of wl1271
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*
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* Copyright (C) 2008-2009 Nokia Corporation
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*
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* Contact: Luciano Coelho <luciano.coelho@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __BOOT_H__
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#define __BOOT_H__
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#include "wl12xx.h"
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int wl1271_boot(struct wl1271 *wl);
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int wl1271_load_firmware(struct wl1271 *wl);
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#define WL1271_NO_SUBBANDS 8
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#define WL1271_NO_POWER_LEVELS 4
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#define WL1271_FW_VERSION_MAX_LEN 20
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struct wl1271_static_data {
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u8 mac_address[ETH_ALEN];
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u8 padding[2];
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u8 fw_version[WL1271_FW_VERSION_MAX_LEN];
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u32 hw_version;
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u8 tx_power_table[WL1271_NO_SUBBANDS][WL1271_NO_POWER_LEVELS];
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};
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/* number of times we try to read the INIT interrupt */
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#define INIT_LOOP 20000
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/* delay between retries */
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#define INIT_LOOP_DELAY 50
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#define WU_COUNTER_PAUSE_VAL 0x3FF
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#define WELP_ARM_COMMAND_VAL 0x4
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#define OCP_REG_POLARITY 0x0064
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#define OCP_REG_CLK_TYPE 0x0448
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#define OCP_REG_CLK_POLARITY 0x0cb2
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#define OCP_REG_CLK_PULL 0x0cb4
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#define REG_FUSE_DATA_2_1 0x050a
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#define PG_VER_MASK 0x3c
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#define PG_VER_OFFSET 2
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#define PG_MAJOR_VER_MASK 0x3
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#define PG_MAJOR_VER_OFFSET 0x0
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#define PG_MINOR_VER_MASK 0xc
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#define PG_MINOR_VER_OFFSET 0x2
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#define CMD_MBOX_ADDRESS 0x407B4
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#define POLARITY_LOW BIT(1)
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#define NO_PULL (BIT(14) | BIT(15))
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#define FREF_CLK_TYPE_BITS 0xfffffe7f
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#define CLK_REQ_PRCM 0x100
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#define FREF_CLK_POLARITY_BITS 0xfffff8ff
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#define CLK_REQ_OUTN_SEL 0x700
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/* PLL configuration algorithm for wl128x */
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#define SYS_CLK_CFG_REG 0x2200
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/* Bit[0] - 0-TCXO, 1-FREF */
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#define MCS_PLL_CLK_SEL_FREF BIT(0)
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/* Bit[3:2] - 01-TCXO, 10-FREF */
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#define WL_CLK_REQ_TYPE_FREF BIT(3)
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#define WL_CLK_REQ_TYPE_PG2 (BIT(3) | BIT(2))
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/* Bit[4] - 0-TCXO, 1-FREF */
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#define PRCM_CM_EN_MUX_WLAN_FREF BIT(4)
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#define TCXO_ILOAD_INT_REG 0x2264
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#define TCXO_CLK_DETECT_REG 0x2266
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#define TCXO_DET_FAILED BIT(4)
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#define FREF_ILOAD_INT_REG 0x2084
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#define FREF_CLK_DETECT_REG 0x2086
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#define FREF_CLK_DETECT_FAIL BIT(4)
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/* Use this reg for masking during driver access */
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#define WL_SPARE_REG 0x2320
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#define WL_SPARE_VAL BIT(2)
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/* Bit[6:5:3] - mask wl write SYS_CLK_CFG[8:5:2:4] */
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#define WL_SPARE_MASK_8526 (BIT(6) | BIT(5) | BIT(3))
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#define PLL_LOCK_COUNTERS_REG 0xD8C
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#define PLL_LOCK_COUNTERS_COEX 0x0F
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#define PLL_LOCK_COUNTERS_MCS 0xF0
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#define MCS_PLL_OVERRIDE_REG 0xD90
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#define MCS_PLL_CONFIG_REG 0xD92
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#define MCS_SEL_IN_FREQ_MASK 0x0070
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#define MCS_SEL_IN_FREQ_SHIFT 4
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#define MCS_PLL_CONFIG_REG_VAL 0x73
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#define MCS_PLL_ENABLE_HP (BIT(0) | BIT(1))
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#define MCS_PLL_M_REG 0xD94
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#define MCS_PLL_N_REG 0xD96
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#define MCS_PLL_M_REG_VAL 0xC8
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#define MCS_PLL_N_REG_VAL 0x07
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#define SDIO_IO_DS 0xd14
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/* SDIO/wSPI DS configuration values */
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enum {
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HCI_IO_DS_8MA = 0,
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HCI_IO_DS_4MA = 1, /* default */
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HCI_IO_DS_6MA = 2,
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HCI_IO_DS_2MA = 3,
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};
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/* end PLL configuration algorithm for wl128x */
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#endif
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