c279b77596
Also select the USB_ARCH_HAS_EHCI symbol in order to make the EHCI driver available. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Kathy Giori <kgiori@qca.qualcomm.com> Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com> Patchwork: https://patchwork.linux-mips.org/patch/2527/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
310 lines
9.5 KiB
C
310 lines
9.5 KiB
C
/*
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* Atheros AR71XX/AR724X/AR913X SoC register definitions
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*
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef __ASM_MACH_AR71XX_REGS_H
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#define __ASM_MACH_AR71XX_REGS_H
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#define AR71XX_APB_BASE 0x18000000
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#define AR71XX_EHCI_BASE 0x1b000000
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#define AR71XX_EHCI_SIZE 0x1000
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#define AR71XX_OHCI_BASE 0x1c000000
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#define AR71XX_OHCI_SIZE 0x1000
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#define AR71XX_SPI_BASE 0x1f000000
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#define AR71XX_SPI_SIZE 0x01000000
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#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
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#define AR71XX_DDR_CTRL_SIZE 0x100
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#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
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#define AR71XX_UART_SIZE 0x100
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#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
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#define AR71XX_USB_CTRL_SIZE 0x100
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#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
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#define AR71XX_GPIO_SIZE 0x100
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#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
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#define AR71XX_PLL_SIZE 0x100
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#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
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#define AR71XX_RESET_SIZE 0x100
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#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
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#define AR7240_USB_CTRL_SIZE 0x100
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#define AR7240_OHCI_BASE 0x1b000000
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#define AR7240_OHCI_SIZE 0x1000
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#define AR724X_EHCI_BASE 0x1b000000
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#define AR724X_EHCI_SIZE 0x1000
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#define AR913X_EHCI_BASE 0x1b000000
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#define AR913X_EHCI_SIZE 0x1000
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#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
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#define AR913X_WMAC_SIZE 0x30000
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#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
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#define AR933X_UART_SIZE 0x14
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#define AR933X_EHCI_BASE 0x1b000000
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#define AR933X_EHCI_SIZE 0x1000
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/*
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* DDR_CTRL block
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*/
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#define AR71XX_DDR_REG_PCI_WIN0 0x7c
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#define AR71XX_DDR_REG_PCI_WIN1 0x80
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#define AR71XX_DDR_REG_PCI_WIN2 0x84
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#define AR71XX_DDR_REG_PCI_WIN3 0x88
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#define AR71XX_DDR_REG_PCI_WIN4 0x8c
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#define AR71XX_DDR_REG_PCI_WIN5 0x90
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#define AR71XX_DDR_REG_PCI_WIN6 0x94
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#define AR71XX_DDR_REG_PCI_WIN7 0x98
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#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
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#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
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#define AR71XX_DDR_REG_FLUSH_USB 0xa4
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#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
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#define AR724X_DDR_REG_FLUSH_GE0 0x7c
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#define AR724X_DDR_REG_FLUSH_GE1 0x80
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#define AR724X_DDR_REG_FLUSH_USB 0x84
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#define AR724X_DDR_REG_FLUSH_PCIE 0x88
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#define AR913X_DDR_REG_FLUSH_GE0 0x7c
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#define AR913X_DDR_REG_FLUSH_GE1 0x80
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#define AR913X_DDR_REG_FLUSH_USB 0x84
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#define AR913X_DDR_REG_FLUSH_WMAC 0x88
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#define AR933X_DDR_REG_FLUSH_GE0 0x7c
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#define AR933X_DDR_REG_FLUSH_GE1 0x80
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#define AR933X_DDR_REG_FLUSH_USB 0x84
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#define AR933X_DDR_REG_FLUSH_WMAC 0x88
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/*
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* PLL block
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*/
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#define AR71XX_PLL_REG_CPU_CONFIG 0x00
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#define AR71XX_PLL_REG_SEC_CONFIG 0x04
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#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
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#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
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#define AR71XX_PLL_DIV_SHIFT 3
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#define AR71XX_PLL_DIV_MASK 0x1f
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#define AR71XX_CPU_DIV_SHIFT 16
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#define AR71XX_CPU_DIV_MASK 0x3
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#define AR71XX_DDR_DIV_SHIFT 18
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#define AR71XX_DDR_DIV_MASK 0x3
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#define AR71XX_AHB_DIV_SHIFT 20
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#define AR71XX_AHB_DIV_MASK 0x7
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#define AR724X_PLL_REG_CPU_CONFIG 0x00
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#define AR724X_PLL_REG_PCIE_CONFIG 0x18
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#define AR724X_PLL_DIV_SHIFT 0
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#define AR724X_PLL_DIV_MASK 0x3ff
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#define AR724X_PLL_REF_DIV_SHIFT 10
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#define AR724X_PLL_REF_DIV_MASK 0xf
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#define AR724X_AHB_DIV_SHIFT 19
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#define AR724X_AHB_DIV_MASK 0x1
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#define AR724X_DDR_DIV_SHIFT 22
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#define AR724X_DDR_DIV_MASK 0x3
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#define AR913X_PLL_REG_CPU_CONFIG 0x00
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#define AR913X_PLL_REG_ETH_CONFIG 0x04
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#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
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#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
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#define AR913X_PLL_DIV_SHIFT 0
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#define AR913X_PLL_DIV_MASK 0x3ff
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#define AR913X_DDR_DIV_SHIFT 22
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#define AR913X_DDR_DIV_MASK 0x3
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#define AR913X_AHB_DIV_SHIFT 19
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#define AR913X_AHB_DIV_MASK 0x1
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#define AR933X_PLL_CPU_CONFIG_REG 0x00
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#define AR933X_PLL_CLOCK_CTRL_REG 0x08
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#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
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#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
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#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
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#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
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#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
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#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
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#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
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#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
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#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
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#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
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#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
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#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
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#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
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/*
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* USB_CONFIG block
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*/
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#define AR71XX_USB_CTRL_REG_FLADJ 0x00
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#define AR71XX_USB_CTRL_REG_CONFIG 0x04
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/*
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* RESET block
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*/
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#define AR71XX_RESET_REG_TIMER 0x00
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#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
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#define AR71XX_RESET_REG_WDOG_CTRL 0x08
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#define AR71XX_RESET_REG_WDOG 0x0c
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#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
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#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
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#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
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#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
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#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
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#define AR71XX_RESET_REG_RESET_MODULE 0x24
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#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
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#define AR71XX_RESET_REG_PERFC0 0x30
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#define AR71XX_RESET_REG_PERFC1 0x34
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#define AR71XX_RESET_REG_REV_ID 0x90
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#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18
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#define AR913X_RESET_REG_RESET_MODULE 0x1c
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#define AR913X_RESET_REG_PERF_CTRL 0x20
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#define AR913X_RESET_REG_PERFC0 0x24
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#define AR913X_RESET_REG_PERFC1 0x28
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#define AR724X_RESET_REG_RESET_MODULE 0x1c
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#define AR933X_RESET_REG_RESET_MODULE 0x1c
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#define AR933X_RESET_REG_BOOTSTRAP 0xac
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#define MISC_INT_ETHSW BIT(12)
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#define MISC_INT_TIMER4 BIT(10)
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#define MISC_INT_TIMER3 BIT(9)
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#define MISC_INT_TIMER2 BIT(8)
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#define MISC_INT_DMA BIT(7)
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#define MISC_INT_OHCI BIT(6)
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#define MISC_INT_PERFC BIT(5)
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#define MISC_INT_WDOG BIT(4)
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#define MISC_INT_UART BIT(3)
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#define MISC_INT_GPIO BIT(2)
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#define MISC_INT_ERROR BIT(1)
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#define MISC_INT_TIMER BIT(0)
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#define AR71XX_RESET_EXTERNAL BIT(28)
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#define AR71XX_RESET_FULL_CHIP BIT(24)
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#define AR71XX_RESET_CPU_NMI BIT(21)
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#define AR71XX_RESET_CPU_COLD BIT(20)
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#define AR71XX_RESET_DMA BIT(19)
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#define AR71XX_RESET_SLIC BIT(18)
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#define AR71XX_RESET_STEREO BIT(17)
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#define AR71XX_RESET_DDR BIT(16)
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#define AR71XX_RESET_GE1_MAC BIT(13)
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#define AR71XX_RESET_GE1_PHY BIT(12)
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#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
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#define AR71XX_RESET_GE0_MAC BIT(9)
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#define AR71XX_RESET_GE0_PHY BIT(8)
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#define AR71XX_RESET_USB_OHCI_DLL BIT(6)
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#define AR71XX_RESET_USB_HOST BIT(5)
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#define AR71XX_RESET_USB_PHY BIT(4)
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#define AR71XX_RESET_PCI_BUS BIT(1)
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#define AR71XX_RESET_PCI_CORE BIT(0)
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#define AR7240_RESET_USB_HOST BIT(5)
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#define AR7240_RESET_OHCI_DLL BIT(3)
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#define AR724X_RESET_GE1_MDIO BIT(23)
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#define AR724X_RESET_GE0_MDIO BIT(22)
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#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
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#define AR724X_RESET_PCIE_PHY BIT(7)
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#define AR724X_RESET_PCIE BIT(6)
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#define AR724X_RESET_USB_HOST BIT(5)
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#define AR724X_RESET_USB_PHY BIT(4)
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#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
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#define AR913X_RESET_AMBA2WMAC BIT(22)
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#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
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#define AR913X_RESET_USB_HOST BIT(5)
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#define AR913X_RESET_USB_PHY BIT(4)
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#define AR933X_RESET_USB_HOST BIT(5)
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#define AR933X_RESET_USB_PHY BIT(4)
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#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
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#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
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#define REV_ID_MAJOR_MASK 0xfff0
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#define REV_ID_MAJOR_AR71XX 0x00a0
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#define REV_ID_MAJOR_AR913X 0x00b0
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#define REV_ID_MAJOR_AR7240 0x00c0
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#define REV_ID_MAJOR_AR7241 0x0100
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#define REV_ID_MAJOR_AR7242 0x1100
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#define REV_ID_MAJOR_AR9330 0x0110
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#define REV_ID_MAJOR_AR9331 0x1110
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#define AR71XX_REV_ID_MINOR_MASK 0x3
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#define AR71XX_REV_ID_MINOR_AR7130 0x0
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#define AR71XX_REV_ID_MINOR_AR7141 0x1
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#define AR71XX_REV_ID_MINOR_AR7161 0x2
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#define AR71XX_REV_ID_REVISION_MASK 0x3
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#define AR71XX_REV_ID_REVISION_SHIFT 2
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#define AR913X_REV_ID_MINOR_MASK 0x3
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#define AR913X_REV_ID_MINOR_AR9130 0x0
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#define AR913X_REV_ID_MINOR_AR9132 0x1
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#define AR913X_REV_ID_REVISION_MASK 0x3
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#define AR913X_REV_ID_REVISION_SHIFT 2
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#define AR933X_REV_ID_REVISION_MASK 0x3
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#define AR724X_REV_ID_REVISION_MASK 0x3
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/*
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* SPI block
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*/
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#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
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#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
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#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
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#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
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#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
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#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */
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#define AR71XX_SPI_CTRL_DIV_MASK 0x3f
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#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
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#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
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#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
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#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
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#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
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#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
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#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
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AR71XX_SPI_IOC_CS2)
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/*
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* GPIO block
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*/
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#define AR71XX_GPIO_REG_OE 0x00
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#define AR71XX_GPIO_REG_IN 0x04
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#define AR71XX_GPIO_REG_OUT 0x08
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#define AR71XX_GPIO_REG_SET 0x0c
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#define AR71XX_GPIO_REG_CLEAR 0x10
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#define AR71XX_GPIO_REG_INT_MODE 0x14
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#define AR71XX_GPIO_REG_INT_TYPE 0x18
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#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
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#define AR71XX_GPIO_REG_INT_PENDING 0x20
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#define AR71XX_GPIO_REG_INT_ENABLE 0x24
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#define AR71XX_GPIO_REG_FUNC 0x28
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#define AR71XX_GPIO_COUNT 16
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#define AR724X_GPIO_COUNT 18
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#define AR913X_GPIO_COUNT 22
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#define AR933X_GPIO_COUNT 30
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#endif /* __ASM_MACH_AR71XX_REGS_H */
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