Jayachandran C c24a8a7a99 MIPS: Netlogic: Add MSI support for XLP ... Add MSI chip and MSIX chip definitions. For MSI, we map the link interrupt to a MSI link IRQ which will do a second level of dispatch based on the MSI status register. The MSI chip definitions use the MSI enable register to enable and disable the MSI irqs. For MSI-X, we split the 32 available MSI-X vectors across the four PCIe links (8 each). These PIC interrupts generate an IRQ per link which uses a second level dispatch as well. The MSI-X chip definition uses the standard functions to enable and disable interrupts. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6270/		2014-01-24 22:39:46 +01:00
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asm	MIPS: Netlogic: Add MSI support for XLP	2014-01-24 22:39:46 +01:00
uapi/asm	MIPS: microMIPS: mfhc1 & mthc1 support for the FPU emulator	2014-01-13 23:40:55 +01:00