c1a2562ac5
This implements support for MSIs on p5ioc2 PHBs. We only support MSIs on the PCIe PHBs, not the PCI-X ones as the later hasn't been properly verified in HW. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
48 lines
1.1 KiB
C
48 lines
1.1 KiB
C
#ifndef __POWERNV_PCI_H
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#define __POWERNV_PCI_H
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struct pci_dn;
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enum pnv_phb_type {
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PNV_PHB_P5IOC2,
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PNV_PHB_IODA1,
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PNV_PHB_IODA2,
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};
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struct pnv_phb {
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struct pci_controller *hose;
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enum pnv_phb_type type;
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u64 opal_id;
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void __iomem *regs;
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spinlock_t lock;
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#ifdef CONFIG_PCI_MSI
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unsigned long *msi_map;
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unsigned int msi_base;
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unsigned int msi_count;
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unsigned int msi_next;
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unsigned int msi32_support;
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#endif
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int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
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unsigned int hwirq, unsigned int is_64,
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struct msi_msg *msg);
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void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
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void (*fixup_phb)(struct pci_controller *hose);
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u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
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union {
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struct {
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struct iommu_table iommu_table;
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} p5ioc2;
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};
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};
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extern struct pci_ops pnv_pci_ops;
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extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
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void *tce_mem, u64 tce_size,
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u64 dma_offset);
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extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
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#endif /* __POWERNV_PCI_H */
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