c14dab5c07
Previous code made an assumption that the power on value of global control MSR has enabled all fixed and general purpose counters properly. However, this is not the case for certain Intel processors, such as Atom - and it might also be firmware dependent. Each enable bit in IA32_PERF_GLOBAL_CTRL is AND'ed with the enable bits for all privilege levels in the respective IA32_PERFEVTSELx or IA32_PERF_FIXED_CTR_CTRL MSRs to start/stop the counting of respective counters. Counting is enabled if the AND'ed results is true; counting is disabled when the result is false. The end result is that all fixed counters are always disabled on Atom processors because the assumption is just invalid. Fix this by not initializing the ctrl-mask out of the global MSR, but setting it to perf_counter_mask. Reported-by: Stephane Eranian <eranian@googlemail.com> Signed-off-by: Yong Wang <yong.y.wang@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> LKML-Reference: <20090624021324.GA2788@ywang-moblin2.bj.intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> |
||
|---|---|---|
| .. | ||
| cpufreq | ||
| mcheck | ||
| mtrr | ||
| .gitignore | ||
| addon_cpuid_features.c | ||
| amd.c | ||
| bugs.c | ||
| bugs_64.c | ||
| centaur.c | ||
| cmpxchg.c | ||
| common.c | ||
| cpu.h | ||
| cpu_debug.c | ||
| cyrix.c | ||
| hypervisor.c | ||
| intel.c | ||
| intel_cacheinfo.c | ||
| Makefile | ||
| mkcapflags.pl | ||
| perf_counter.c | ||
| perfctr-watchdog.c | ||
| powerflags.c | ||
| proc.c | ||
| transmeta.c | ||
| umc.c | ||
| vmware.c | ||