bf792094ef
The driver currently ignores the local or remote link faults raised at the mac layer. This patch fixes it. Our mac however only advertizes link events, so wait for the phy to stabilize the link, then enable mac link events interrupts. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
652 lines
19 KiB
C
652 lines
19 KiB
C
/*
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* Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "common.h"
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#include "regs.h"
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/*
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* # of exact address filters. The first one is used for the station address,
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* the rest are available for multicast addresses.
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*/
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#define EXACT_ADDR_FILTERS 8
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static inline int macidx(const struct cmac *mac)
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{
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return mac->offset / (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR);
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}
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static void xaui_serdes_reset(struct cmac *mac)
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{
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static const unsigned int clear[] = {
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F_PWRDN0 | F_PWRDN1, F_RESETPLL01, F_RESET0 | F_RESET1,
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F_PWRDN2 | F_PWRDN3, F_RESETPLL23, F_RESET2 | F_RESET3
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};
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int i;
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struct adapter *adap = mac->adapter;
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u32 ctrl = A_XGM_SERDES_CTRL0 + mac->offset;
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t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] |
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F_RESET3 | F_RESET2 | F_RESET1 | F_RESET0 |
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F_PWRDN3 | F_PWRDN2 | F_PWRDN1 | F_PWRDN0 |
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F_RESETPLL23 | F_RESETPLL01);
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t3_read_reg(adap, ctrl);
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udelay(15);
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for (i = 0; i < ARRAY_SIZE(clear); i++) {
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t3_set_reg_field(adap, ctrl, clear[i], 0);
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udelay(15);
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}
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}
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void t3b_pcs_reset(struct cmac *mac)
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{
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t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
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F_PCS_RESET_, 0);
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udelay(20);
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t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset, 0,
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F_PCS_RESET_);
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}
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int t3_mac_reset(struct cmac *mac)
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{
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static const struct addr_val_pair mac_reset_avp[] = {
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{A_XGM_TX_CTRL, 0},
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{A_XGM_RX_CTRL, 0},
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{A_XGM_RX_CFG, F_DISPAUSEFRAMES | F_EN1536BFRAMES |
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F_RMFCS | F_ENJUMBO | F_ENHASHMCAST},
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{A_XGM_RX_HASH_LOW, 0},
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{A_XGM_RX_HASH_HIGH, 0},
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{A_XGM_RX_EXACT_MATCH_LOW_1, 0},
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{A_XGM_RX_EXACT_MATCH_LOW_2, 0},
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{A_XGM_RX_EXACT_MATCH_LOW_3, 0},
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{A_XGM_RX_EXACT_MATCH_LOW_4, 0},
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{A_XGM_RX_EXACT_MATCH_LOW_5, 0},
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{A_XGM_RX_EXACT_MATCH_LOW_6, 0},
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{A_XGM_RX_EXACT_MATCH_LOW_7, 0},
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{A_XGM_RX_EXACT_MATCH_LOW_8, 0},
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{A_XGM_STAT_CTRL, F_CLRSTATS}
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};
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u32 val;
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struct adapter *adap = mac->adapter;
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unsigned int oft = mac->offset;
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t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
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t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
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t3_write_regs(adap, mac_reset_avp, ARRAY_SIZE(mac_reset_avp), oft);
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t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + oft,
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F_RXSTRFRWRD | F_DISERRFRAMES,
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uses_xaui(adap) ? 0 : F_RXSTRFRWRD);
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t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft, 0, F_UNDERUNFIX);
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if (uses_xaui(adap)) {
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if (adap->params.rev == 0) {
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t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
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F_RXENABLE | F_TXENABLE);
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if (t3_wait_op_done(adap, A_XGM_SERDES_STATUS1 + oft,
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F_CMULOCK, 1, 5, 2)) {
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CH_ERR(adap,
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"MAC %d XAUI SERDES CMU lock failed\n",
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macidx(mac));
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return -1;
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}
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t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
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F_SERDESRESET_);
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} else
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xaui_serdes_reset(mac);
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}
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t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + oft,
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V_RXMAXFRAMERSIZE(M_RXMAXFRAMERSIZE),
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V_RXMAXFRAMERSIZE(MAX_FRAME_SIZE) | F_RXENFRAMER);
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val = F_MAC_RESET_ | F_XGMAC_STOP_EN;
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if (is_10G(adap))
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val |= F_PCS_RESET_;
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else if (uses_xaui(adap))
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val |= F_PCS_RESET_ | F_XG2G_RESET_;
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else
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val |= F_RGMII_RESET_ | F_XG2G_RESET_;
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t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
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t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
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if ((val & F_PCS_RESET_) && adap->params.rev) {
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msleep(1);
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t3b_pcs_reset(mac);
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}
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memset(&mac->stats, 0, sizeof(mac->stats));
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return 0;
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}
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static int t3b2_mac_reset(struct cmac *mac)
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{
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struct adapter *adap = mac->adapter;
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unsigned int oft = mac->offset, store;
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int idx = macidx(mac);
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u32 val;
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if (!macidx(mac))
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t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0);
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else
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t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
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/* Stop NIC traffic to reduce the number of TXTOGGLES */
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t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, 0);
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/* Ensure TX drains */
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t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN, 0);
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t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
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t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
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/* Store A_TP_TX_DROP_CFG_CH0 */
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t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
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store = t3_read_reg(adap, A_TP_TX_DROP_CFG_CH0 + idx);
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msleep(10);
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/* Change DROP_CFG to 0xc0000011 */
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t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
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t3_write_reg(adap, A_TP_PIO_DATA, 0xc0000011);
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/* Check for xgm Rx fifo empty */
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/* Increased loop count to 1000 from 5 cover 1G and 100Mbps case */
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if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft,
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0x80000000, 1, 1000, 2)) {
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CH_ERR(adap, "MAC %d Rx fifo drain failed\n",
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macidx(mac));
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return -1;
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}
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t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0);
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t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
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val = F_MAC_RESET_;
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if (is_10G(adap))
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val |= F_PCS_RESET_;
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else if (uses_xaui(adap))
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val |= F_PCS_RESET_ | F_XG2G_RESET_;
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else
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val |= F_RGMII_RESET_ | F_XG2G_RESET_;
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t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
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t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
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if ((val & F_PCS_RESET_) && adap->params.rev) {
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msleep(1);
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t3b_pcs_reset(mac);
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}
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t3_write_reg(adap, A_XGM_RX_CFG + oft,
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F_DISPAUSEFRAMES | F_EN1536BFRAMES |
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F_RMFCS | F_ENJUMBO | F_ENHASHMCAST);
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/* Restore the DROP_CFG */
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t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
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t3_write_reg(adap, A_TP_PIO_DATA, store);
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if (!idx)
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t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT0ACTIVE);
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else
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t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT1ACTIVE);
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/* re-enable nic traffic */
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t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, 1);
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/* Set: re-enable NIC traffic */
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t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, 1);
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return 0;
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}
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/*
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* Set the exact match register 'idx' to recognize the given Ethernet address.
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*/
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static void set_addr_filter(struct cmac *mac, int idx, const u8 * addr)
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{
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u32 addr_lo, addr_hi;
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unsigned int oft = mac->offset + idx * 8;
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addr_lo = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
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addr_hi = (addr[5] << 8) | addr[4];
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t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1 + oft, addr_lo);
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t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_HIGH_1 + oft, addr_hi);
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}
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/* Set one of the station's unicast MAC addresses. */
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int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6])
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{
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if (idx >= mac->nucast)
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return -EINVAL;
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set_addr_filter(mac, idx, addr);
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return 0;
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}
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/*
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* Specify the number of exact address filters that should be reserved for
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* unicast addresses. Caller should reload the unicast and multicast addresses
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* after calling this.
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*/
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int t3_mac_set_num_ucast(struct cmac *mac, int n)
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{
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if (n > EXACT_ADDR_FILTERS)
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return -EINVAL;
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mac->nucast = n;
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return 0;
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}
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void t3_mac_disable_exact_filters(struct cmac *mac)
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{
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unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_LOW_1;
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for (i = 0; i < EXACT_ADDR_FILTERS; i++, reg += 8) {
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u32 v = t3_read_reg(mac->adapter, reg);
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t3_write_reg(mac->adapter, reg, v);
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}
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t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */
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}
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void t3_mac_enable_exact_filters(struct cmac *mac)
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{
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unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_HIGH_1;
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for (i = 0; i < EXACT_ADDR_FILTERS; i++, reg += 8) {
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u32 v = t3_read_reg(mac->adapter, reg);
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t3_write_reg(mac->adapter, reg, v);
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}
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t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */
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}
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/* Calculate the RX hash filter index of an Ethernet address */
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static int hash_hw_addr(const u8 * addr)
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{
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int hash = 0, octet, bit, i = 0, c;
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for (octet = 0; octet < 6; ++octet)
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for (c = addr[octet], bit = 0; bit < 8; c >>= 1, ++bit) {
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hash ^= (c & 1) << i;
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if (++i == 6)
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i = 0;
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}
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return hash;
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}
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int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm)
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{
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u32 val, hash_lo, hash_hi;
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struct adapter *adap = mac->adapter;
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unsigned int oft = mac->offset;
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val = t3_read_reg(adap, A_XGM_RX_CFG + oft) & ~F_COPYALLFRAMES;
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if (rm->dev->flags & IFF_PROMISC)
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val |= F_COPYALLFRAMES;
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t3_write_reg(adap, A_XGM_RX_CFG + oft, val);
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if (rm->dev->flags & IFF_ALLMULTI)
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hash_lo = hash_hi = 0xffffffff;
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else {
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u8 *addr;
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int exact_addr_idx = mac->nucast;
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hash_lo = hash_hi = 0;
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while ((addr = t3_get_next_mcaddr(rm)))
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if (exact_addr_idx < EXACT_ADDR_FILTERS)
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set_addr_filter(mac, exact_addr_idx++, addr);
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else {
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int hash = hash_hw_addr(addr);
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if (hash < 32)
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hash_lo |= (1 << hash);
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else
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hash_hi |= (1 << (hash - 32));
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}
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}
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t3_write_reg(adap, A_XGM_RX_HASH_LOW + oft, hash_lo);
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t3_write_reg(adap, A_XGM_RX_HASH_HIGH + oft, hash_hi);
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return 0;
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}
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static int rx_fifo_hwm(int mtu)
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{
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int hwm;
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hwm = max(MAC_RXFIFO_SIZE - 3 * mtu, (MAC_RXFIFO_SIZE * 38) / 100);
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return min(hwm, MAC_RXFIFO_SIZE - 8192);
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}
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int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
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{
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int hwm, lwm, divisor;
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int ipg;
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unsigned int thres, v, reg;
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struct adapter *adap = mac->adapter;
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/*
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* MAX_FRAME_SIZE inludes header + FCS, mtu doesn't. The HW max
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* packet size register includes header, but not FCS.
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*/
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mtu += 14;
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if (mtu > MAX_FRAME_SIZE - 4)
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return -EINVAL;
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t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
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if (adap->params.rev >= T3_REV_B2 &&
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(t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) {
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t3_mac_disable_exact_filters(mac);
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v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
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t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset,
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F_ENHASHMCAST | F_COPYALLFRAMES, F_DISBCAST);
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reg = adap->params.rev == T3_REV_B2 ?
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A_XGM_RX_MAX_PKT_SIZE_ERR_CNT : A_XGM_RXFIFO_CFG;
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/* drain RX FIFO */
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if (t3_wait_op_done(adap, reg + mac->offset,
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F_RXFIFO_EMPTY, 1, 20, 5)) {
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t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
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t3_mac_enable_exact_filters(mac);
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return -EIO;
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}
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t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
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V_RXMAXPKTSIZE(M_RXMAXPKTSIZE),
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V_RXMAXPKTSIZE(mtu));
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t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
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t3_mac_enable_exact_filters(mac);
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} else
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t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
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V_RXMAXPKTSIZE(M_RXMAXPKTSIZE),
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V_RXMAXPKTSIZE(mtu));
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/*
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* Adjust the PAUSE frame watermarks. We always set the LWM, and the
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* HWM only if flow-control is enabled.
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*/
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hwm = rx_fifo_hwm(mtu);
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lwm = min(3 * (int)mtu, MAC_RXFIFO_SIZE / 4);
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v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
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v &= ~V_RXFIFOPAUSELWM(M_RXFIFOPAUSELWM);
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v |= V_RXFIFOPAUSELWM(lwm / 8);
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if (G_RXFIFOPAUSEHWM(v))
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v = (v & ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM)) |
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V_RXFIFOPAUSEHWM(hwm / 8);
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t3_write_reg(adap, A_XGM_RXFIFO_CFG + mac->offset, v);
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/* Adjust the TX FIFO threshold based on the MTU */
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thres = (adap->params.vpd.cclk * 1000) / 15625;
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thres = (thres * mtu) / 1000;
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if (is_10G(adap))
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thres /= 10;
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thres = mtu > thres ? (mtu - thres + 7) / 8 : 0;
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thres = max(thres, 8U); /* need at least 8 */
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ipg = (adap->params.rev == T3_REV_C) ? 0 : 1;
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t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
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V_TXFIFOTHRESH(M_TXFIFOTHRESH) | V_TXIPG(M_TXIPG),
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V_TXFIFOTHRESH(thres) | V_TXIPG(ipg));
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if (adap->params.rev > 0) {
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divisor = (adap->params.rev == T3_REV_C) ? 64 : 8;
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t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
|
|
(hwm - lwm) * 4 / divisor);
|
|
}
|
|
t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
|
|
MAC_RXFIFO_SIZE * 4 * 8 / 512);
|
|
return 0;
|
|
}
|
|
|
|
int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
|
|
{
|
|
u32 val;
|
|
struct adapter *adap = mac->adapter;
|
|
unsigned int oft = mac->offset;
|
|
|
|
if (duplex >= 0 && duplex != DUPLEX_FULL)
|
|
return -EINVAL;
|
|
if (speed >= 0) {
|
|
if (speed == SPEED_10)
|
|
val = V_PORTSPEED(0);
|
|
else if (speed == SPEED_100)
|
|
val = V_PORTSPEED(1);
|
|
else if (speed == SPEED_1000)
|
|
val = V_PORTSPEED(2);
|
|
else if (speed == SPEED_10000)
|
|
val = V_PORTSPEED(3);
|
|
else
|
|
return -EINVAL;
|
|
|
|
t3_set_reg_field(adap, A_XGM_PORT_CFG + oft,
|
|
V_PORTSPEED(M_PORTSPEED), val);
|
|
}
|
|
|
|
val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
|
|
val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM);
|
|
if (fc & PAUSE_TX)
|
|
val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(
|
|
t3_read_reg(adap,
|
|
A_XGM_RX_MAX_PKT_SIZE
|
|
+ oft)) / 8);
|
|
t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
|
|
|
|
t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
|
|
(fc & PAUSE_RX) ? F_TXPAUSEEN : 0);
|
|
return 0;
|
|
}
|
|
|
|
int t3_mac_enable(struct cmac *mac, int which)
|
|
{
|
|
int idx = macidx(mac);
|
|
struct adapter *adap = mac->adapter;
|
|
unsigned int oft = mac->offset;
|
|
struct mac_stats *s = &mac->stats;
|
|
|
|
if (which & MAC_DIRECTION_TX) {
|
|
t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
|
|
t3_write_reg(adap, A_TP_PIO_DATA,
|
|
adap->params.rev == T3_REV_C ?
|
|
0xc4ffff01 : 0xc0ede401);
|
|
t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
|
|
t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx,
|
|
adap->params.rev == T3_REV_C ? 0 : 1 << idx);
|
|
|
|
t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
|
|
|
|
t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);
|
|
mac->tx_mcnt = s->tx_frames;
|
|
mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
|
|
A_TP_PIO_DATA)));
|
|
mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
|
|
A_XGM_TX_SPI4_SOP_EOP_CNT +
|
|
oft)));
|
|
mac->rx_mcnt = s->rx_frames;
|
|
mac->rx_pause = s->rx_pause;
|
|
mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
|
|
A_XGM_RX_SPI4_SOP_EOP_CNT +
|
|
oft)));
|
|
mac->rx_ocnt = s->rx_fifo_ovfl;
|
|
mac->txen = F_TXEN;
|
|
mac->toggle_cnt = 0;
|
|
}
|
|
if (which & MAC_DIRECTION_RX)
|
|
t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
|
|
return 0;
|
|
}
|
|
|
|
int t3_mac_disable(struct cmac *mac, int which)
|
|
{
|
|
struct adapter *adap = mac->adapter;
|
|
|
|
if (which & MAC_DIRECTION_TX) {
|
|
t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
|
|
mac->txen = 0;
|
|
}
|
|
if (which & MAC_DIRECTION_RX) {
|
|
int val = F_MAC_RESET_;
|
|
|
|
t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
|
|
F_PCS_RESET_, 0);
|
|
msleep(100);
|
|
t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
|
|
if (is_10G(adap))
|
|
val |= F_PCS_RESET_;
|
|
else if (uses_xaui(adap))
|
|
val |= F_PCS_RESET_ | F_XG2G_RESET_;
|
|
else
|
|
val |= F_RGMII_RESET_ | F_XG2G_RESET_;
|
|
t3_write_reg(mac->adapter, A_XGM_RESET_CTRL + mac->offset, val);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int t3b2_mac_watchdog_task(struct cmac *mac)
|
|
{
|
|
struct adapter *adap = mac->adapter;
|
|
struct mac_stats *s = &mac->stats;
|
|
unsigned int tx_tcnt, tx_xcnt;
|
|
u64 tx_mcnt = s->tx_frames;
|
|
int status;
|
|
|
|
status = 0;
|
|
tx_xcnt = 1; /* By default tx_xcnt is making progress */
|
|
tx_tcnt = mac->tx_tcnt; /* If tx_mcnt is progressing ignore tx_tcnt */
|
|
if (tx_mcnt == mac->tx_mcnt && mac->rx_pause == s->rx_pause) {
|
|
tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
|
|
A_XGM_TX_SPI4_SOP_EOP_CNT +
|
|
mac->offset)));
|
|
if (tx_xcnt == 0) {
|
|
t3_write_reg(adap, A_TP_PIO_ADDR,
|
|
A_TP_TX_DROP_CNT_CH0 + macidx(mac));
|
|
tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
|
|
A_TP_PIO_DATA)));
|
|
} else {
|
|
goto out;
|
|
}
|
|
} else {
|
|
mac->toggle_cnt = 0;
|
|
goto out;
|
|
}
|
|
|
|
if ((tx_tcnt != mac->tx_tcnt) && (mac->tx_xcnt == 0)) {
|
|
if (mac->toggle_cnt > 4) {
|
|
status = 2;
|
|
goto out;
|
|
} else {
|
|
status = 1;
|
|
goto out;
|
|
}
|
|
} else {
|
|
mac->toggle_cnt = 0;
|
|
goto out;
|
|
}
|
|
|
|
out:
|
|
mac->tx_tcnt = tx_tcnt;
|
|
mac->tx_xcnt = tx_xcnt;
|
|
mac->tx_mcnt = s->tx_frames;
|
|
mac->rx_pause = s->rx_pause;
|
|
if (status == 1) {
|
|
t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
|
|
t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */
|
|
t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, mac->txen);
|
|
t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */
|
|
mac->toggle_cnt++;
|
|
} else if (status == 2) {
|
|
t3b2_mac_reset(mac);
|
|
mac->toggle_cnt = 0;
|
|
}
|
|
return status;
|
|
}
|
|
|
|
/*
|
|
* This function is called periodically to accumulate the current values of the
|
|
* RMON counters into the port statistics. Since the packet counters are only
|
|
* 32 bits they can overflow in ~286 secs at 10G, so the function should be
|
|
* called more frequently than that. The byte counters are 45-bit wide, they
|
|
* would overflow in ~7.8 hours.
|
|
*/
|
|
const struct mac_stats *t3_mac_update_stats(struct cmac *mac)
|
|
{
|
|
#define RMON_READ(mac, addr) t3_read_reg(mac->adapter, addr + mac->offset)
|
|
#define RMON_UPDATE(mac, name, reg) \
|
|
(mac)->stats.name += (u64)RMON_READ(mac, A_XGM_STAT_##reg)
|
|
#define RMON_UPDATE64(mac, name, reg_lo, reg_hi) \
|
|
(mac)->stats.name += RMON_READ(mac, A_XGM_STAT_##reg_lo) + \
|
|
((u64)RMON_READ(mac, A_XGM_STAT_##reg_hi) << 32)
|
|
|
|
u32 v, lo;
|
|
|
|
RMON_UPDATE64(mac, rx_octets, RX_BYTES_LOW, RX_BYTES_HIGH);
|
|
RMON_UPDATE64(mac, rx_frames, RX_FRAMES_LOW, RX_FRAMES_HIGH);
|
|
RMON_UPDATE(mac, rx_mcast_frames, RX_MCAST_FRAMES);
|
|
RMON_UPDATE(mac, rx_bcast_frames, RX_BCAST_FRAMES);
|
|
RMON_UPDATE(mac, rx_fcs_errs, RX_CRC_ERR_FRAMES);
|
|
RMON_UPDATE(mac, rx_pause, RX_PAUSE_FRAMES);
|
|
RMON_UPDATE(mac, rx_jabber, RX_JABBER_FRAMES);
|
|
RMON_UPDATE(mac, rx_short, RX_SHORT_FRAMES);
|
|
RMON_UPDATE(mac, rx_symbol_errs, RX_SYM_CODE_ERR_FRAMES);
|
|
|
|
RMON_UPDATE(mac, rx_too_long, RX_OVERSIZE_FRAMES);
|
|
|
|
v = RMON_READ(mac, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT);
|
|
if (mac->adapter->params.rev == T3_REV_B2)
|
|
v &= 0x7fffffff;
|
|
mac->stats.rx_too_long += v;
|
|
|
|
RMON_UPDATE(mac, rx_frames_64, RX_64B_FRAMES);
|
|
RMON_UPDATE(mac, rx_frames_65_127, RX_65_127B_FRAMES);
|
|
RMON_UPDATE(mac, rx_frames_128_255, RX_128_255B_FRAMES);
|
|
RMON_UPDATE(mac, rx_frames_256_511, RX_256_511B_FRAMES);
|
|
RMON_UPDATE(mac, rx_frames_512_1023, RX_512_1023B_FRAMES);
|
|
RMON_UPDATE(mac, rx_frames_1024_1518, RX_1024_1518B_FRAMES);
|
|
RMON_UPDATE(mac, rx_frames_1519_max, RX_1519_MAXB_FRAMES);
|
|
|
|
RMON_UPDATE64(mac, tx_octets, TX_BYTE_LOW, TX_BYTE_HIGH);
|
|
RMON_UPDATE64(mac, tx_frames, TX_FRAME_LOW, TX_FRAME_HIGH);
|
|
RMON_UPDATE(mac, tx_mcast_frames, TX_MCAST);
|
|
RMON_UPDATE(mac, tx_bcast_frames, TX_BCAST);
|
|
RMON_UPDATE(mac, tx_pause, TX_PAUSE);
|
|
/* This counts error frames in general (bad FCS, underrun, etc). */
|
|
RMON_UPDATE(mac, tx_underrun, TX_ERR_FRAMES);
|
|
|
|
RMON_UPDATE(mac, tx_frames_64, TX_64B_FRAMES);
|
|
RMON_UPDATE(mac, tx_frames_65_127, TX_65_127B_FRAMES);
|
|
RMON_UPDATE(mac, tx_frames_128_255, TX_128_255B_FRAMES);
|
|
RMON_UPDATE(mac, tx_frames_256_511, TX_256_511B_FRAMES);
|
|
RMON_UPDATE(mac, tx_frames_512_1023, TX_512_1023B_FRAMES);
|
|
RMON_UPDATE(mac, tx_frames_1024_1518, TX_1024_1518B_FRAMES);
|
|
RMON_UPDATE(mac, tx_frames_1519_max, TX_1519_MAXB_FRAMES);
|
|
|
|
/* The next stat isn't clear-on-read. */
|
|
t3_write_reg(mac->adapter, A_TP_MIB_INDEX, mac->offset ? 51 : 50);
|
|
v = t3_read_reg(mac->adapter, A_TP_MIB_RDATA);
|
|
lo = (u32) mac->stats.rx_cong_drops;
|
|
mac->stats.rx_cong_drops += (u64) (v - lo);
|
|
|
|
return &mac->stats;
|
|
}
|