4bb0d3ec3e
i386 Inline asm cleanup. Use cr/dr accessor functions.
Also, a potential bugfix. Also, some CR accessors really should be volatile.
Reads from CR0 (numeric state may change in an exception handler), writes to
CR4 (flipping CR4.TSD) and reads from CR2 (page fault) prevent instruction
re-ordering. I did not add memory clobber to CR3 / CR4 / CR0 updates, as it
was not there to begin with, and in no case should kernel memory be clobbered,
except when doing a TLB flush, which already has memory clobber.
I noticed that page invalidation does not have a memory clobber. I can't find
a bug as a result, but there is definitely a potential for a bug here:
#define __flush_tlb_single(addr) \
__asm__ __volatile__("invlpg %0": :"m" (*(char *) addr))
Signed-off-by: Zachary Amsden <zach@vmware.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
216 lines
5.4 KiB
C
216 lines
5.4 KiB
C
/*
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* include/asm-i386/bugs.h
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*
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* Copyright (C) 1994 Linus Torvalds
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*
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* Cyrix stuff, June 1998 by:
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* - Rafael R. Reilova (moved everything from head.S),
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* <rreilova@ececs.uc.edu>
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* - Channing Corn (tests & fixes),
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* - Andrew D. Balsa (code cleanup).
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*
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* Pentium III FXSR, SSE support
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* Gareth Hughes <gareth@valinux.com>, May 2000
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*/
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/*
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* This is included by init/main.c to check for architecture-dependent bugs.
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*
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* Needs:
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* void check_bugs(void);
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <asm/processor.h>
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#include <asm/i387.h>
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#include <asm/msr.h>
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static int __init no_halt(char *s)
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{
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boot_cpu_data.hlt_works_ok = 0;
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return 1;
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}
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__setup("no-hlt", no_halt);
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static int __init mca_pentium(char *s)
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{
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mca_pentium_flag = 1;
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return 1;
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}
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__setup("mca-pentium", mca_pentium);
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static int __init no_387(char *s)
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{
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boot_cpu_data.hard_math = 0;
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write_cr0(0xE | read_cr0());
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return 1;
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}
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__setup("no387", no_387);
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static double __initdata x = 4195835.0;
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static double __initdata y = 3145727.0;
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/*
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* This used to check for exceptions..
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* However, it turns out that to support that,
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* the XMM trap handlers basically had to
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* be buggy. So let's have a correct XMM trap
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* handler, and forget about printing out
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* some status at boot.
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*
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* We should really only care about bugs here
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* anyway. Not features.
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*/
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static void __init check_fpu(void)
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{
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if (!boot_cpu_data.hard_math) {
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#ifndef CONFIG_MATH_EMULATION
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printk(KERN_EMERG "No coprocessor found and no math emulation present.\n");
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printk(KERN_EMERG "Giving up.\n");
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for (;;) ;
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#endif
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return;
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}
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/* Enable FXSR and company _before_ testing for FP problems. */
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/*
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* Verify that the FXSAVE/FXRSTOR data will be 16-byte aligned.
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*/
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if (offsetof(struct task_struct, thread.i387.fxsave) & 15) {
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extern void __buggy_fxsr_alignment(void);
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__buggy_fxsr_alignment();
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}
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if (cpu_has_fxsr) {
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printk(KERN_INFO "Enabling fast FPU save and restore... ");
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set_in_cr4(X86_CR4_OSFXSR);
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printk("done.\n");
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}
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if (cpu_has_xmm) {
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printk(KERN_INFO "Enabling unmasked SIMD FPU exception support... ");
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set_in_cr4(X86_CR4_OSXMMEXCPT);
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printk("done.\n");
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}
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/* Test for the divl bug.. */
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__asm__("fninit\n\t"
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"fldl %1\n\t"
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"fdivl %2\n\t"
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"fmull %2\n\t"
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"fldl %1\n\t"
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"fsubp %%st,%%st(1)\n\t"
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"fistpl %0\n\t"
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"fwait\n\t"
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"fninit"
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: "=m" (*&boot_cpu_data.fdiv_bug)
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: "m" (*&x), "m" (*&y));
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if (boot_cpu_data.fdiv_bug)
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printk("Hmm, FPU with FDIV bug.\n");
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}
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static void __init check_hlt(void)
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{
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printk(KERN_INFO "Checking 'hlt' instruction... ");
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if (!boot_cpu_data.hlt_works_ok) {
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printk("disabled\n");
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return;
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}
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halt();
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halt();
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halt();
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halt();
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printk("OK.\n");
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}
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/*
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* Most 386 processors have a bug where a POPAD can lock the
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* machine even from user space.
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*/
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static void __init check_popad(void)
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{
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#ifndef CONFIG_X86_POPAD_OK
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int res, inp = (int) &res;
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printk(KERN_INFO "Checking for popad bug... ");
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__asm__ __volatile__(
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"movl $12345678,%%eax; movl $0,%%edi; pusha; popa; movl (%%edx,%%edi),%%ecx "
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: "=&a" (res)
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: "d" (inp)
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: "ecx", "edi" );
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/* If this fails, it means that any user program may lock the CPU hard. Too bad. */
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if (res != 12345678) printk( "Buggy.\n" );
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else printk( "OK.\n" );
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#endif
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}
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/*
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* Check whether we are able to run this kernel safely on SMP.
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*
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* - In order to run on a i386, we need to be compiled for i386
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* (for due to lack of "invlpg" and working WP on a i386)
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* - In order to run on anything without a TSC, we need to be
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* compiled for a i486.
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* - In order to support the local APIC on a buggy Pentium machine,
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* we need to be compiled with CONFIG_X86_GOOD_APIC disabled,
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* which happens implicitly if compiled for a Pentium or lower
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* (unless an advanced selection of CPU features is used) as an
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* otherwise config implies a properly working local APIC without
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* the need to do extra reads from the APIC.
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*/
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static void __init check_config(void)
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{
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/*
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* We'd better not be a i386 if we're configured to use some
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* i486+ only features! (WP works in supervisor mode and the
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* new "invlpg" and "bswap" instructions)
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*/
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#if defined(CONFIG_X86_WP_WORKS_OK) || defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_BSWAP)
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if (boot_cpu_data.x86 == 3)
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panic("Kernel requires i486+ for 'invlpg' and other features");
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#endif
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/*
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* If we configured ourselves for a TSC, we'd better have one!
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*/
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#ifdef CONFIG_X86_TSC
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if (!cpu_has_tsc)
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panic("Kernel compiled for Pentium+, requires TSC feature!");
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#endif
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/*
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* If we were told we had a good local APIC, check for buggy Pentia,
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* i.e. all B steppings and the C2 stepping of P54C when using their
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* integrated APIC (see 11AP erratum in "Pentium Processor
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* Specification Update").
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*/
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#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_GOOD_APIC)
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if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL
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&& cpu_has_apic
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&& boot_cpu_data.x86 == 5
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&& boot_cpu_data.x86_model == 2
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&& (boot_cpu_data.x86_mask < 6 || boot_cpu_data.x86_mask == 11))
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panic("Kernel compiled for PMMX+, assumes a local APIC without the read-before-write bug!");
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#endif
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}
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extern void alternative_instructions(void);
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static void __init check_bugs(void)
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{
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identify_cpu(&boot_cpu_data);
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#ifndef CONFIG_SMP
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printk("CPU: ");
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print_cpu_info(&boot_cpu_data);
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#endif
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check_config();
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check_fpu();
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check_hlt();
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check_popad();
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system_utsname.machine[1] = '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
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alternative_instructions();
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}
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