e9c08f0d57
The documentation for the S3C6410 CPU voltage scaling is rather unclear, with omitted values for several speed settings. Originally the code was using only quoted values, resulting in some fairly odd settings. The S3C6410 is also unusual in that the both the maximum and minimum voltages quoted scale as the frequency rises, rather than just the minimum voltage. Clean this up a bit by always using the specified typical settings as the minimum voltage (ignoring any specified minimum voltage) in order to avoid running near the edge of the processor capabilities. Also use the next quoted maximum voltages rather than the typical voltages where no maximum voltage is quoted, allowing operation on a greater range of systems. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
270 lines
6.3 KiB
C
270 lines
6.3 KiB
C
/* linux/arch/arm/plat-s3c64xx/cpufreq.c
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*
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* Copyright 2009 Wolfson Microelectronics plc
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*
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* S3C64xx CPUfreq Support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/regulator/consumer.h>
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static struct clk *armclk;
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static struct regulator *vddarm;
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static unsigned long regulator_latency;
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#ifdef CONFIG_CPU_S3C6410
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struct s3c64xx_dvfs {
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unsigned int vddarm_min;
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unsigned int vddarm_max;
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};
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static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
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[0] = { 1000000, 1150000 },
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[1] = { 1050000, 1150000 },
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[2] = { 1100000, 1150000 },
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[3] = { 1200000, 1350000 },
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};
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static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
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{ 0, 66000 },
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{ 0, 133000 },
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{ 1, 222000 },
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{ 1, 266000 },
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{ 2, 333000 },
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{ 2, 400000 },
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{ 2, 532000 },
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{ 2, 533000 },
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{ 3, 667000 },
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{ 0, CPUFREQ_TABLE_END },
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};
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#endif
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static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy)
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{
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if (policy->cpu != 0)
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return -EINVAL;
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return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table);
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}
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static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
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{
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if (cpu != 0)
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return 0;
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return clk_get_rate(armclk) / 1000;
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}
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static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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int ret;
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unsigned int i;
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struct cpufreq_freqs freqs;
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struct s3c64xx_dvfs *dvfs;
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ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
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target_freq, relation, &i);
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if (ret != 0)
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return ret;
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freqs.cpu = 0;
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freqs.old = clk_get_rate(armclk) / 1000;
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freqs.new = s3c64xx_freq_table[i].frequency;
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freqs.flags = 0;
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dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index];
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if (freqs.old == freqs.new)
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return 0;
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pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new);
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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#ifdef CONFIG_REGULATOR
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if (vddarm && freqs.new > freqs.old) {
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ret = regulator_set_voltage(vddarm,
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dvfs->vddarm_min,
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dvfs->vddarm_max);
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if (ret != 0) {
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pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
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freqs.new, ret);
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goto err;
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}
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}
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#endif
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ret = clk_set_rate(armclk, freqs.new * 1000);
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if (ret < 0) {
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pr_err("cpufreq: Failed to set rate %dkHz: %d\n",
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freqs.new, ret);
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goto err;
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}
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#ifdef CONFIG_REGULATOR
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if (vddarm && freqs.new < freqs.old) {
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ret = regulator_set_voltage(vddarm,
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dvfs->vddarm_min,
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dvfs->vddarm_max);
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if (ret != 0) {
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pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
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freqs.new, ret);
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goto err_clk;
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}
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}
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#endif
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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pr_debug("cpufreq: Set actual frequency %lukHz\n",
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clk_get_rate(armclk) / 1000);
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return 0;
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err_clk:
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if (clk_set_rate(armclk, freqs.old * 1000) < 0)
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pr_err("Failed to restore original clock rate\n");
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err:
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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return ret;
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}
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#ifdef CONFIG_REGULATOR
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static void __init s3c64xx_cpufreq_config_regulator(void)
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{
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int count, v, i, found;
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struct cpufreq_frequency_table *freq;
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struct s3c64xx_dvfs *dvfs;
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count = regulator_count_voltages(vddarm);
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if (count < 0) {
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pr_err("cpufreq: Unable to check supported voltages\n");
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}
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freq = s3c64xx_freq_table;
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while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
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if (freq->frequency == CPUFREQ_ENTRY_INVALID)
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continue;
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dvfs = &s3c64xx_dvfs_table[freq->index];
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found = 0;
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for (i = 0; i < count; i++) {
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v = regulator_list_voltage(vddarm, i);
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if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
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found = 1;
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}
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if (!found) {
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pr_debug("cpufreq: %dkHz unsupported by regulator\n",
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freq->frequency);
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freq->frequency = CPUFREQ_ENTRY_INVALID;
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}
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freq++;
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}
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/* Guess based on having to do an I2C/SPI write; in future we
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* will be able to query the regulator performance here. */
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regulator_latency = 1 * 1000 * 1000;
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}
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#endif
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static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
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{
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int ret;
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struct cpufreq_frequency_table *freq;
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if (policy->cpu != 0)
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return -EINVAL;
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if (s3c64xx_freq_table == NULL) {
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pr_err("cpufreq: No frequency information for this CPU\n");
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return -ENODEV;
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}
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armclk = clk_get(NULL, "armclk");
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if (IS_ERR(armclk)) {
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pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n",
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PTR_ERR(armclk));
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return PTR_ERR(armclk);
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}
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#ifdef CONFIG_REGULATOR
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vddarm = regulator_get(NULL, "vddarm");
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if (IS_ERR(vddarm)) {
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ret = PTR_ERR(vddarm);
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pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
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pr_err("cpufreq: Only frequency scaling available\n");
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vddarm = NULL;
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} else {
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s3c64xx_cpufreq_config_regulator();
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}
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#endif
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freq = s3c64xx_freq_table;
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while (freq->frequency != CPUFREQ_TABLE_END) {
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unsigned long r;
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/* Check for frequencies we can generate */
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r = clk_round_rate(armclk, freq->frequency * 1000);
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r /= 1000;
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if (r != freq->frequency) {
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pr_debug("cpufreq: %dkHz unsupported by clock\n",
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freq->frequency);
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freq->frequency = CPUFREQ_ENTRY_INVALID;
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}
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/* If we have no regulator then assume startup
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* frequency is the maximum we can support. */
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if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0))
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freq->frequency = CPUFREQ_ENTRY_INVALID;
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freq++;
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}
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policy->cur = clk_get_rate(armclk) / 1000;
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/* Datasheet says PLL stabalisation time (if we were to use
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* the PLLs, which we don't currently) is ~300us worst case,
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* but add some fudge.
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*/
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policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency;
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ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
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if (ret != 0) {
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pr_err("cpufreq: Failed to configure frequency table: %d\n",
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ret);
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regulator_put(vddarm);
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clk_put(armclk);
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}
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return ret;
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}
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static struct cpufreq_driver s3c64xx_cpufreq_driver = {
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.owner = THIS_MODULE,
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.flags = 0,
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.verify = s3c64xx_cpufreq_verify_speed,
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.target = s3c64xx_cpufreq_set_target,
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.get = s3c64xx_cpufreq_get_speed,
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.init = s3c64xx_cpufreq_driver_init,
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.name = "s3c",
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};
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static int __init s3c64xx_cpufreq_init(void)
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{
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return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
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}
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module_init(s3c64xx_cpufreq_init);
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