1ec1e82f25
This patch adds support for the Freescale i.MX SDMA engine. The SDMA engine is a scatter/gather DMA engine which is implemented as a seperate coprocessor. SDMA needs its own firmware which is requested using the standard request_firmware mechanism. The firmware has different entry points for each peripheral type, so drivers have to pass the peripheral type to the DMA engine which in turn picks the correct firmware entry point from a table contained in the firmware image itself. The original Freescale code also supports support for transfering data to the internal SRAM which needs different entry points to the firmware. Support for this is currently not implemented. Also, support for the ASRC (asymmetric sample rate converter) is skipped. I took a very simple approach to implement dmaengine support. Only a single descriptor is statically assigned to a each channel. This means that transfers can't be queued up but only a single transfer is in progress. This simplifies implementation a lot and is sufficient for the usual device/memory transfers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Linus Walleij <linus.ml.walleij@gmail.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
103 lines
3.1 KiB
C
103 lines
3.1 KiB
C
/*
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* linux/arch/arm/mach-imx/include/mach/dma-v1.h
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*
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* i.MX DMA registration and IRQ dispatching
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*
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* Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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* Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
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* Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __MACH_DMA_V1_H__
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#define __MACH_DMA_V1_H__
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#define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
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#include <mach/dma.h>
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#define IMX_DMA_CHANNELS 16
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#define DMA_MODE_READ 0
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#define DMA_MODE_WRITE 1
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#define DMA_MODE_MASK 1
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#define MX1_DMA_REG(offset) MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
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/* DMA Interrupt Mask Register */
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#define MX1_DMA_DIMR MX1_DMA_REG(0x08)
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/* Channel Control Register */
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#define MX1_DMA_CCR(x) MX1_DMA_REG(0x8c + ((x) << 6))
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#define IMX_DMA_MEMSIZE_32 (0 << 4)
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#define IMX_DMA_MEMSIZE_8 (1 << 4)
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#define IMX_DMA_MEMSIZE_16 (2 << 4)
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#define IMX_DMA_TYPE_LINEAR (0 << 10)
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#define IMX_DMA_TYPE_2D (1 << 10)
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#define IMX_DMA_TYPE_FIFO (2 << 10)
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#define IMX_DMA_ERR_BURST (1 << 0)
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#define IMX_DMA_ERR_REQUEST (1 << 1)
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#define IMX_DMA_ERR_TRANSFER (1 << 2)
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#define IMX_DMA_ERR_BUFFER (1 << 3)
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#define IMX_DMA_ERR_TIMEOUT (1 << 4)
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int
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imx_dma_config_channel(int channel, unsigned int config_port,
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unsigned int config_mem, unsigned int dmareq, int hw_chaining);
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void
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imx_dma_config_burstlen(int channel, unsigned int burstlen);
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int
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imx_dma_setup_single(int channel, dma_addr_t dma_address,
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unsigned int dma_length, unsigned int dev_addr,
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unsigned int dmamode);
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/*
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* Use this flag as the dma_length argument to imx_dma_setup_sg()
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* to create an endless running dma loop. The end of the scatterlist
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* must be linked to the beginning for this to work.
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*/
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#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
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int
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imx_dma_setup_sg(int channel, struct scatterlist *sg,
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unsigned int sgcount, unsigned int dma_length,
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unsigned int dev_addr, unsigned int dmamode);
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int
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imx_dma_setup_handlers(int channel,
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void (*irq_handler) (int, void *),
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void (*err_handler) (int, void *, int), void *data);
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int
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imx_dma_setup_progression_handler(int channel,
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void (*prog_handler) (int, void*, struct scatterlist*));
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void imx_dma_enable(int channel);
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void imx_dma_disable(int channel);
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int imx_dma_request(int channel, const char *name);
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void imx_dma_free(int channel);
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int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
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#endif /* __MACH_DMA_V1_H__ */
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