bbf2ba67cd
BMIPS438x has a 64-byte D$ line size and BMIPS5000 has a 128-byte L2 line size. If L1_CACHE_SHIFT is undersized, DMA buffers will not be cacheline-aligned and terrible things will happen. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8164/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
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avr32 | ||
blackfin | ||
c6x | ||
cris | ||
frv | ||
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ia64 | ||
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m68k | ||
metag | ||
microblaze | ||
mips | ||
mn10300 | ||
openrisc | ||
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score | ||
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unicore32 | ||
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xtensa | ||
.gitignore | ||
Kconfig |