b9f69f4f4a
Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Tested-by: Robert Reif <reif@earthlink.net> Signed-off-by: David S. Miller <davem@davemloft.net>
50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
#ifndef ___ASM_SPARC_DMA_MAPPING_H
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#define ___ASM_SPARC_DMA_MAPPING_H
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#if defined(__sparc__) && defined(__arch64__)
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#include <asm/dma-mapping_64.h>
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#else
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#include <asm/dma-mapping_32.h>
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#endif
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#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
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extern int dma_supported(struct device *dev, u64 mask);
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extern int dma_set_mask(struct device *dev, u64 dma_mask);
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static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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return (dma_addr == DMA_ERROR_CODE);
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}
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static inline int dma_get_cache_alignment(void)
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{
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/*
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* no easy way to get cache size on all processors, so return
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* the maximum possible, to be safe
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*/
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return (1 << INTERNODE_CACHE_SHIFT);
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}
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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#define dma_is_consistent(d, h) (1)
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static inline void dma_sync_single_range_for_cpu(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset,
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size_t size,
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enum dma_data_direction dir)
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{
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dma_sync_single_for_cpu(dev, dma_handle+offset, size, dir);
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}
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static inline void dma_sync_single_range_for_device(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset,
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size_t size,
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enum dma_data_direction dir)
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{
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dma_sync_single_for_device(dev, dma_handle+offset, size, dir);
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}
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#endif
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