Sekhar Nori b987c4b2c9 davinci: am18x/da850/omap-l138: keep async clock constant with cpufreq ... Keep PLL0 SYSCLK3 at a constant rate of 100MHz. This enables the AEMIF timing to remain valid even as the PLL0 output is changed by cpufreq driver to save power. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>		2010-09-24 07:40:25 -07:00
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mach	davinci: am18x/da850/omap-l138: keep async clock constant with cpufreq	2010-09-24 07:40:25 -07:00