3d5134ee83
This rewrites pretty much from scratch the handling of MMIO and PIO space allocations on powerpc64. The main goals are: - Get rid of imalloc and use more common code where possible - Simplify the current mess so that PIO space is allocated and mapped in a single place for PCI bridges - Handle allocation constraints of PIO for all bridges including hot plugged ones within the 2GB space reserved for IO ports, so that devices on hotplugged busses will now work with drivers that assume IO ports fit in an int. - Cleanup and separate tracking of the ISA space in the reserved low 64K of IO space. No ISA -> Nothing mapped there. I booted a cell blade with IDE on PIO and MMIO and a dual G5 so far, that's it :-) With this patch, all allocations are done using the code in mm/vmalloc.c, though we use the low level __get_vm_area with explicit start/stop constraints in order to manage separate areas for vmalloc/vmap, ioremap, and PCI IOs. This greatly simplifies a lot of things, as you can see in the diffstat of that patch :-) A new pair of functions pcibios_map/unmap_io_space() now replace all of the previous code that used to manipulate PCI IOs space. The allocation is done at mapping time, which is now called from scan_phb's, just before the devices are probed (instead of after, which is by itself a bug fix). The only other caller is the PCI hotplug code for hot adding PCI-PCI bridges (slots). imalloc is gone, as is the "sub-allocation" thing, but I do beleive that hotplug should still work in the sense that the space allocation is always done by the PHB, but if you unmap a child bus of this PHB (which seems to be possible), then the code should properly tear down all the HPTE mappings for that area of the PHB allocated IO space. I now always reserve the first 64K of IO space for the bridge with the ISA bus on it. I have moved the code for tracking ISA in a separate file which should also make it smarter if we ever are capable of hot unplugging or re-plugging an ISA bridge. This should have a side effect on platforms like powermac where VGA IOs will no longer work. This is done on purpose though as they would have worked semi-randomly before. The idea at this point is to isolate drivers that might need to access those and fix them by providing a proper function to obtain an offset to the legacy IOs of a given bus. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
180 lines
4.1 KiB
C
180 lines
4.1 KiB
C
/*
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* Copyright (C) 2006 PA Semi, Inc
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*
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* Authors: Kip Walker, PA Semi
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* Olof Johansson, PA Semi
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*
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* Maintained by: Olof Johansson <olof@lixom.net>
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*
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* Based on arch/powerpc/platforms/maple/pci.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/ppc-pci.h>
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#define PA_PXP_CFA(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
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static inline int pa_pxp_offset_valid(u8 bus, u8 devfn, int offset)
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{
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/* Device 0 Function 0 is special: It's config space spans function 1 as
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* well, so allow larger offset. It's really a two-function device but the
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* second function does not probe.
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*/
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if (bus == 0 && devfn == 0)
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return offset < 8192;
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else
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return offset < 4096;
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}
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static void volatile __iomem *pa_pxp_cfg_addr(struct pci_controller *hose,
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u8 bus, u8 devfn, int offset)
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{
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return hose->cfg_data + PA_PXP_CFA(bus, devfn, offset);
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}
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static int pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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struct pci_controller *hose;
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void volatile __iomem *addr;
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hose = pci_bus_to_host(bus);
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if (!hose)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (!pa_pxp_offset_valid(bus->number, devfn, offset))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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switch (len) {
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case 1:
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*val = in_8(addr);
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break;
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case 2:
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*val = in_le16(addr);
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break;
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default:
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*val = in_le32(addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int pa_pxp_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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struct pci_controller *hose;
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void volatile __iomem *addr;
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hose = pci_bus_to_host(bus);
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if (!hose)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (!pa_pxp_offset_valid(bus->number, devfn, offset))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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switch (len) {
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case 1:
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out_8(addr, val);
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(void) in_8(addr);
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break;
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case 2:
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out_le16(addr, val);
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(void) in_le16(addr);
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break;
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default:
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out_le32(addr, val);
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(void) in_le32(addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops pa_pxp_ops = {
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pa_pxp_read_config,
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pa_pxp_write_config,
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};
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static void __init setup_pa_pxp(struct pci_controller *hose)
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{
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hose->ops = &pa_pxp_ops;
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hose->cfg_data = ioremap(0xe0000000, 0x10000000);
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}
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static int __init add_bridge(struct device_node *dev)
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{
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struct pci_controller *hose;
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pr_debug("Adding PCI host bridge %s\n", dev->full_name);
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hose = pcibios_alloc_controller(dev);
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if (!hose)
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return -ENOMEM;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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setup_pa_pxp(hose);
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printk(KERN_INFO "Found PA-PXP PCI host bridge.\n");
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/* Interpret the "ranges" property */
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pci_process_bridge_OF_ranges(hose, dev, 1);
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return 0;
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}
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void __init pas_pci_init(void)
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{
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struct device_node *np, *root;
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root = of_find_node_by_path("/");
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if (!root) {
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printk(KERN_CRIT "pas_pci_init: can't find root "
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"of device tree\n");
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return;
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}
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for (np = NULL; (np = of_get_next_child(root, np)) != NULL;)
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if (np->name && !strcmp(np->name, "pxp") && !add_bridge(np))
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of_node_get(np);
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of_node_put(root);
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/* Setup the linkage between OF nodes and PHBs */
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pci_devs_phb_init();
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/* Use the common resource allocation mechanism */
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pci_probe_only = 1;
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}
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