b8853aa3d9
Loongson doesn't support MIPSR2, therefore, MIPSR2 vectored interrupts (cpu_has_vint) and MIPSR2 external interrupt controller mode (cpu_has_veic) are 0. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1112/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
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cs5536 | ||
cpu-feature-overrides.h | ||
dma-coherence.h | ||
loongson.h | ||
machine.h | ||
mc146818rtc.h | ||
mem.h | ||
pci.h | ||
war.h |