5a88130a2a
Select PINCTRL_TZ1090_PDC from SOC_TZ1090 to enable the PDC pin controller driver once it is merged, and instantiate it from tz1090.dtsi. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Grant Likely <grant.likely@linaro.org>
67 lines
1.5 KiB
Text
67 lines
1.5 KiB
Text
choice
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prompt "SoC Type"
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default META21_FPGA
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config META12_FPGA
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bool "Meta 1.2 FPGA"
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select METAG_META12
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help
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This is a Meta 1.2 FPGA bitstream, just a bare CPU.
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config META21_FPGA
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bool "Meta 2.1 FPGA"
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select METAG_META21
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help
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This is a Meta 2.1 FPGA bitstream, just a bare CPU.
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config SOC_TZ1090
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bool "Toumaz Xenif TZ1090 SoC (Comet)"
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select METAG_LNKGET_AROUND_CACHE
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select METAG_META21
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select METAG_SMP_WRITE_REORDERING
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select PINCTRL
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select PINCTRL_TZ1090
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select PINCTRL_TZ1090_PDC
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help
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This is a Toumaz Technology Xenif TZ1090 (A.K.A. Comet) SoC containing
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a 2-threaded HTP.
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endchoice
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menu "SoC configuration"
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if METAG_META21
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# Meta 2.x specific options
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config METAG_META21_MMU
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bool "Meta 2.x MMU mode"
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default y
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help
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Use the Meta 2.x MMU in extended mode.
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config METAG_UNALIGNED
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bool "Meta 2.x unaligned access checking"
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default y
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help
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All memory accesses will be checked for alignment and an exception
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raised on unaligned accesses. This feature does cost performance
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but without it there will be no notification of this type of error.
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config METAG_USER_TCM
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bool "Meta on-chip memory support for userland"
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select GENERIC_ALLOCATOR
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default y
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help
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Allow the on-chip memories of Meta SoCs to be used by user
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applications.
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endif
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config METAG_HALT_ON_PANIC
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bool "Halt the core on panic"
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help
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Halt the core when a panic occurs. This is useful when running
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pre-production silicon or in an FPGA environment.
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endmenu
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