2a5fdc9add
In tegra*.dtsi, set status="disable" for all HW modules that the board design may choose not to use. Update all boards to specifically enable any of those modules that are useful by setting status="okay". This makes board files say which features they do use, rather than which they don't, which feels more logical. It also makes the .dts files slightly smaller, at least for existing content. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
271 lines
5.8 KiB
Text
271 lines
5.8 KiB
Text
/include/ "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "nvidia,tegra30";
|
|
interrupt-parent = <&intc>;
|
|
|
|
intc: interrupt-controller {
|
|
compatible = "arm,cortex-a9-gic";
|
|
reg = <0x50041000 0x1000
|
|
0x50040100 0x0100>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
|
|
apbdma: dma {
|
|
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
|
|
reg = <0x6000a000 0x1400>;
|
|
interrupts = <0 104 0x04
|
|
0 105 0x04
|
|
0 106 0x04
|
|
0 107 0x04
|
|
0 108 0x04
|
|
0 109 0x04
|
|
0 110 0x04
|
|
0 111 0x04
|
|
0 112 0x04
|
|
0 113 0x04
|
|
0 114 0x04
|
|
0 115 0x04
|
|
0 116 0x04
|
|
0 117 0x04
|
|
0 118 0x04
|
|
0 119 0x04
|
|
0 128 0x04
|
|
0 129 0x04
|
|
0 130 0x04
|
|
0 131 0x04
|
|
0 132 0x04
|
|
0 133 0x04
|
|
0 134 0x04
|
|
0 135 0x04
|
|
0 136 0x04
|
|
0 137 0x04
|
|
0 138 0x04
|
|
0 139 0x04
|
|
0 140 0x04
|
|
0 141 0x04
|
|
0 142 0x04
|
|
0 143 0x04>;
|
|
};
|
|
|
|
ahb: ahb {
|
|
compatible = "nvidia,tegra30-ahb";
|
|
reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
|
|
};
|
|
|
|
gpio: gpio {
|
|
compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
|
|
reg = <0x6000d000 0x1000>;
|
|
interrupts = <0 32 0x04
|
|
0 33 0x04
|
|
0 34 0x04
|
|
0 35 0x04
|
|
0 55 0x04
|
|
0 87 0x04
|
|
0 89 0x04
|
|
0 125 0x04>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
pinmux: pinmux {
|
|
compatible = "nvidia,tegra30-pinmux";
|
|
reg = <0x70000868 0xd0 /* Pad control registers */
|
|
0x70003000 0x3e0>; /* Mux registers */
|
|
};
|
|
|
|
serial@70006000 {
|
|
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
|
reg = <0x70006000 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <0 36 0x04>;
|
|
status = "disable";
|
|
};
|
|
|
|
serial@70006040 {
|
|
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
|
reg = <0x70006040 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <0 37 0x04>;
|
|
status = "disable";
|
|
};
|
|
|
|
serial@70006200 {
|
|
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
|
reg = <0x70006200 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <0 46 0x04>;
|
|
status = "disable";
|
|
};
|
|
|
|
serial@70006300 {
|
|
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
|
reg = <0x70006300 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <0 90 0x04>;
|
|
status = "disable";
|
|
};
|
|
|
|
serial@70006400 {
|
|
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
|
reg = <0x70006400 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <0 91 0x04>;
|
|
status = "disable";
|
|
};
|
|
|
|
i2c@7000c000 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000c000 0x100>;
|
|
interrupts = <0 38 0x04>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disable";
|
|
};
|
|
|
|
i2c@7000c400 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000c400 0x100>;
|
|
interrupts = <0 84 0x04>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disable";
|
|
};
|
|
|
|
i2c@7000c500 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000c500 0x100>;
|
|
interrupts = <0 92 0x04>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disable";
|
|
};
|
|
|
|
i2c@7000c700 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000c700 0x100>;
|
|
interrupts = <0 120 0x04>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disable";
|
|
};
|
|
|
|
i2c@7000d000 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000d000 0x100>;
|
|
interrupts = <0 53 0x04>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disable";
|
|
};
|
|
|
|
pmc {
|
|
compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
|
|
reg = <0x7000e400 0x400>;
|
|
};
|
|
|
|
mc {
|
|
compatible = "nvidia,tegra30-mc";
|
|
reg = <0x7000f000 0x010
|
|
0x7000f03c 0x1b4
|
|
0x7000f200 0x028
|
|
0x7000f284 0x17c>;
|
|
interrupts = <0 77 0x04>;
|
|
};
|
|
|
|
smmu {
|
|
compatible = "nvidia,tegra30-smmu";
|
|
reg = <0x7000f010 0x02c
|
|
0x7000f1f0 0x010
|
|
0x7000f228 0x05c>;
|
|
nvidia,#asids = <4>; /* # of ASIDs */
|
|
dma-window = <0 0x40000000>; /* IOVA start & length */
|
|
nvidia,ahb = <&ahb>;
|
|
};
|
|
|
|
ahub {
|
|
compatible = "nvidia,tegra30-ahub";
|
|
reg = <0x70080000 0x200
|
|
0x70080200 0x100>;
|
|
interrupts = <0 103 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 1>;
|
|
|
|
ranges;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
tegra_i2s0: i2s@70080300 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080300 0x100>;
|
|
nvidia,ahub-cif-ids = <4 4>;
|
|
status = "disable";
|
|
};
|
|
|
|
tegra_i2s1: i2s@70080400 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080400 0x100>;
|
|
nvidia,ahub-cif-ids = <5 5>;
|
|
status = "disable";
|
|
};
|
|
|
|
tegra_i2s2: i2s@70080500 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080500 0x100>;
|
|
nvidia,ahub-cif-ids = <6 6>;
|
|
status = "disable";
|
|
};
|
|
|
|
tegra_i2s3: i2s@70080600 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080600 0x100>;
|
|
nvidia,ahub-cif-ids = <7 7>;
|
|
status = "disable";
|
|
};
|
|
|
|
tegra_i2s4: i2s@70080700 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080700 0x100>;
|
|
nvidia,ahub-cif-ids = <8 8>;
|
|
status = "disable";
|
|
};
|
|
};
|
|
|
|
sdhci@78000000 {
|
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
|
reg = <0x78000000 0x200>;
|
|
interrupts = <0 14 0x04>;
|
|
status = "disable";
|
|
};
|
|
|
|
sdhci@78000200 {
|
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
|
reg = <0x78000200 0x200>;
|
|
interrupts = <0 15 0x04>;
|
|
status = "disable";
|
|
};
|
|
|
|
sdhci@78000400 {
|
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
|
reg = <0x78000400 0x200>;
|
|
interrupts = <0 19 0x04>;
|
|
status = "disable";
|
|
};
|
|
|
|
sdhci@78000600 {
|
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
|
reg = <0x78000600 0x200>;
|
|
interrupts = <0 31 0x04>;
|
|
status = "disable";
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a9-pmu";
|
|
interrupts = <0 144 0x04
|
|
0 145 0x04
|
|
0 146 0x04
|
|
0 147 0x04>;
|
|
};
|
|
};
|