eb7bd9c461
The handling of updating the [DI]MEM_CONTROL MMRs does not follow proper sync procedures as laid out in the Blackfin programming manual. So rather than audit/fix every call location, create helper functions that do the right things in order to safely update these MMRs. Then convert all call sites to use these new helper functions. While we're fixing the code, drop the workaround for anomaly 05000125 as that anomaly applies to old versions of silicon that we do not support. Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
71 lines
2 KiB
C
71 lines
2 KiB
C
/*
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/cpu.h>
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#include <asm/cacheflush.h>
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#include <asm/blackfin.h>
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#include <asm/cplb.h>
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#include <asm/cplbinit.h>
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#if defined(CONFIG_BFIN_ICACHE)
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void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
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{
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unsigned long ctrl;
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int i;
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for (i = 0; i < MAX_CPLBS; i++) {
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bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);
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bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);
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}
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ctrl = bfin_read_IMEM_CONTROL();
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ctrl |= IMC | ENICPLB;
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/* CSYNC to ensure load store ordering */
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CSYNC();
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bfin_write_IMEM_CONTROL(ctrl);
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SSYNC();
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}
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#endif
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#if defined(CONFIG_BFIN_DCACHE)
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void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
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{
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unsigned long ctrl;
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int i;
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for (i = 0; i < MAX_CPLBS; i++) {
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bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr);
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bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data);
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}
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ctrl = bfin_read_DMEM_CONTROL();
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/*
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* Anomaly notes:
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* 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
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* register, so that the port preferences for DAG0 and DAG1 are set
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* to port B
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*/
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ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);
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/* CSYNC to ensure load store ordering */
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CSYNC();
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bfin_write_DMEM_CONTROL(ctrl);
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SSYNC();
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}
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#endif
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