693 lines
19 KiB
C
693 lines
19 KiB
C
/*
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* Support for the interrupt controllers found on Power Macintosh,
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* currently Apple's "Grand Central" interrupt controller in all
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* it's incarnations. OpenPIC support used on newer machines is
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* in a separate file
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*
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* Copyright (C) 1997 Paul Mackerras (paulus@cs.anu.edu.au)
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*
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* Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/config.h>
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/sysdev.h>
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#include <linux/adb.h>
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#include <linux/pmu.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/smp.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/time.h>
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#include <asm/open_pic.h>
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#include <asm/xmon.h>
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#include <asm/pmac_feature.h>
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#include <asm/machdep.h>
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#include "pmac_pic.h"
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/*
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* XXX this should be in xmon.h, but putting it there means xmon.h
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* has to include <linux/interrupt.h> (to get irqreturn_t), which
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* causes all sorts of problems. -- paulus
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*/
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extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
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struct pmac_irq_hw {
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unsigned int event;
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unsigned int enable;
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unsigned int ack;
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unsigned int level;
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};
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/* Default addresses */
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static volatile struct pmac_irq_hw *pmac_irq_hw[4] = {
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(struct pmac_irq_hw *) 0xf3000020,
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(struct pmac_irq_hw *) 0xf3000010,
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(struct pmac_irq_hw *) 0xf4000020,
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(struct pmac_irq_hw *) 0xf4000010,
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};
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#define GC_LEVEL_MASK 0x3ff00000
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#define OHARE_LEVEL_MASK 0x1ff00000
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#define HEATHROW_LEVEL_MASK 0x1ff00000
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static int max_irqs;
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static int max_real_irqs;
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static u32 level_mask[4];
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static DEFINE_SPINLOCK(pmac_pic_lock);
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#define GATWICK_IRQ_POOL_SIZE 10
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static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
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#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
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static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
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/*
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* Mark an irq as "lost". This is only used on the pmac
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* since it can lose interrupts (see pmac_set_irq_mask).
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* -- Cort
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*/
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void
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__set_lost(unsigned long irq_nr, int nokick)
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{
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if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
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atomic_inc(&ppc_n_lost_interrupts);
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if (!nokick)
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set_dec(1);
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}
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}
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static void
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pmac_mask_and_ack_irq(unsigned int irq_nr)
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{
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unsigned long bit = 1UL << (irq_nr & 0x1f);
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int i = irq_nr >> 5;
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unsigned long flags;
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if ((unsigned)irq_nr >= max_irqs)
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return;
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clear_bit(irq_nr, ppc_cached_irq_mask);
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if (test_and_clear_bit(irq_nr, ppc_lost_interrupts))
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atomic_dec(&ppc_n_lost_interrupts);
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spin_lock_irqsave(&pmac_pic_lock, flags);
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out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
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out_le32(&pmac_irq_hw[i]->ack, bit);
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do {
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/* make sure ack gets to controller before we enable
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interrupts */
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mb();
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} while((in_le32(&pmac_irq_hw[i]->enable) & bit)
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!= (ppc_cached_irq_mask[i] & bit));
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spin_unlock_irqrestore(&pmac_pic_lock, flags);
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}
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static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
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{
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unsigned long bit = 1UL << (irq_nr & 0x1f);
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int i = irq_nr >> 5;
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unsigned long flags;
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if ((unsigned)irq_nr >= max_irqs)
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return;
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spin_lock_irqsave(&pmac_pic_lock, flags);
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/* enable unmasked interrupts */
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out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
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do {
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/* make sure mask gets to controller before we
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return to user */
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mb();
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} while((in_le32(&pmac_irq_hw[i]->enable) & bit)
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!= (ppc_cached_irq_mask[i] & bit));
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/*
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* Unfortunately, setting the bit in the enable register
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* when the device interrupt is already on *doesn't* set
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* the bit in the flag register or request another interrupt.
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*/
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if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
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__set_lost((ulong)irq_nr, nokicklost);
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spin_unlock_irqrestore(&pmac_pic_lock, flags);
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}
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/* When an irq gets requested for the first client, if it's an
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* edge interrupt, we clear any previous one on the controller
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*/
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static unsigned int pmac_startup_irq(unsigned int irq_nr)
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{
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unsigned long bit = 1UL << (irq_nr & 0x1f);
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int i = irq_nr >> 5;
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if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
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out_le32(&pmac_irq_hw[i]->ack, bit);
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set_bit(irq_nr, ppc_cached_irq_mask);
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pmac_set_irq_mask(irq_nr, 0);
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return 0;
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}
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static void pmac_mask_irq(unsigned int irq_nr)
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{
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clear_bit(irq_nr, ppc_cached_irq_mask);
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pmac_set_irq_mask(irq_nr, 0);
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mb();
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}
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static void pmac_unmask_irq(unsigned int irq_nr)
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{
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set_bit(irq_nr, ppc_cached_irq_mask);
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pmac_set_irq_mask(irq_nr, 0);
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}
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static void pmac_end_irq(unsigned int irq_nr)
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{
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if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
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&& irq_desc[irq_nr].action) {
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set_bit(irq_nr, ppc_cached_irq_mask);
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pmac_set_irq_mask(irq_nr, 1);
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}
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}
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struct hw_interrupt_type pmac_pic = {
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.typename = " PMAC-PIC ",
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.startup = pmac_startup_irq,
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.enable = pmac_unmask_irq,
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.disable = pmac_mask_irq,
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.ack = pmac_mask_and_ack_irq,
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.end = pmac_end_irq,
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};
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struct hw_interrupt_type gatwick_pic = {
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.typename = " GATWICK ",
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.startup = pmac_startup_irq,
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.enable = pmac_unmask_irq,
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.disable = pmac_mask_irq,
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.ack = pmac_mask_and_ack_irq,
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.end = pmac_end_irq,
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};
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static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
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{
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int irq, bits;
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for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
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int i = irq >> 5;
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bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
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/* We must read level interrupts from the level register */
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bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
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bits &= ppc_cached_irq_mask[i];
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if (bits == 0)
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continue;
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irq += __ilog2(bits);
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__do_IRQ(irq, regs);
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return IRQ_HANDLED;
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}
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printk("gatwick irq not from gatwick pic\n");
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return IRQ_NONE;
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}
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int
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pmac_get_irq(struct pt_regs *regs)
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{
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int irq;
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unsigned long bits = 0;
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#ifdef CONFIG_SMP
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void psurge_smp_message_recv(struct pt_regs *);
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/* IPI's are a hack on the powersurge -- Cort */
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if ( smp_processor_id() != 0 ) {
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psurge_smp_message_recv(regs);
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return -2; /* ignore, already handled */
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}
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#endif /* CONFIG_SMP */
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for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
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int i = irq >> 5;
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bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
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/* We must read level interrupts from the level register */
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bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
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bits &= ppc_cached_irq_mask[i];
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if (bits == 0)
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continue;
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irq += __ilog2(bits);
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break;
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}
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return irq;
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}
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/* This routine will fix some missing interrupt values in the device tree
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* on the gatwick mac-io controller used by some PowerBooks
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*/
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static void __init
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pmac_fix_gatwick_interrupts(struct device_node *gw, int irq_base)
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{
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struct device_node *node;
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int count;
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memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
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node = gw->child;
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count = 0;
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while(node)
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{
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/* Fix SCC */
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if (strcasecmp(node->name, "escc") == 0)
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if (node->child) {
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if (node->child->n_intrs < 3) {
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node->child->intrs = &gatwick_int_pool[count];
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count += 3;
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}
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node->child->n_intrs = 3;
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node->child->intrs[0].line = 15+irq_base;
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node->child->intrs[1].line = 4+irq_base;
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node->child->intrs[2].line = 5+irq_base;
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printk(KERN_INFO "irq: fixed SCC on second controller (%d,%d,%d)\n",
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node->child->intrs[0].line,
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node->child->intrs[1].line,
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node->child->intrs[2].line);
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}
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/* Fix media-bay & left SWIM */
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if (strcasecmp(node->name, "media-bay") == 0) {
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struct device_node* ya_node;
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if (node->n_intrs == 0)
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node->intrs = &gatwick_int_pool[count++];
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node->n_intrs = 1;
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node->intrs[0].line = 29+irq_base;
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printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n",
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node->intrs[0].line);
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ya_node = node->child;
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while(ya_node)
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{
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if (strcasecmp(ya_node->name, "floppy") == 0) {
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if (ya_node->n_intrs < 2) {
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ya_node->intrs = &gatwick_int_pool[count];
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count += 2;
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}
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ya_node->n_intrs = 2;
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ya_node->intrs[0].line = 19+irq_base;
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ya_node->intrs[1].line = 1+irq_base;
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printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
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ya_node->intrs[0].line, ya_node->intrs[1].line);
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}
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if (strcasecmp(ya_node->name, "ata4") == 0) {
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if (ya_node->n_intrs < 2) {
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ya_node->intrs = &gatwick_int_pool[count];
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count += 2;
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}
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ya_node->n_intrs = 2;
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ya_node->intrs[0].line = 14+irq_base;
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ya_node->intrs[1].line = 3+irq_base;
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printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
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ya_node->intrs[0].line, ya_node->intrs[1].line);
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}
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ya_node = ya_node->sibling;
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}
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}
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node = node->sibling;
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}
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if (count > 10) {
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printk("WARNING !! Gatwick interrupt pool overflow\n");
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printk(" GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE);
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printk(" requested = %d\n", count);
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}
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}
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/*
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* The PowerBook 3400/2400/3500 can have a combo ethernet/modem
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* card which includes an ohare chip that acts as a second interrupt
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* controller. If we find this second ohare, set it up and fix the
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* interrupt value in the device tree for the ethernet chip.
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*/
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static int __init enable_second_ohare(void)
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{
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unsigned char bus, devfn;
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unsigned short cmd;
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unsigned long addr;
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struct device_node *irqctrler = find_devices("pci106b,7");
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struct device_node *ether;
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if (irqctrler == NULL || irqctrler->n_addrs <= 0)
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return -1;
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addr = (unsigned long) ioremap(irqctrler->addrs[0].address, 0x40);
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pmac_irq_hw[1] = (volatile struct pmac_irq_hw *)(addr + 0x20);
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max_irqs = 64;
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if (pci_device_from_OF_node(irqctrler, &bus, &devfn) == 0) {
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struct pci_controller* hose = pci_find_hose_for_OF_device(irqctrler);
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if (!hose)
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printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
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else {
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early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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cmd &= ~PCI_COMMAND_IO;
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early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
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}
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}
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/* Fix interrupt for the modem/ethernet combo controller. The number
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in the device tree (27) is bogus (correct for the ethernet-only
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board but not the combo ethernet/modem board).
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The real interrupt is 28 on the second controller -> 28+32 = 60.
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*/
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ether = find_devices("pci1011,14");
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if (ether && ether->n_intrs > 0) {
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ether->intrs[0].line = 60;
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printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n",
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ether->intrs[0].line);
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}
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/* Return the interrupt number of the cascade */
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return irqctrler->intrs[0].line;
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}
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#ifdef CONFIG_POWER4
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static irqreturn_t k2u3_action(int cpl, void *dev_id, struct pt_regs *regs)
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{
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int irq;
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irq = openpic2_get_irq(regs);
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if (irq != -1)
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__do_IRQ(irq, regs);
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return IRQ_HANDLED;
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}
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static struct irqaction k2u3_cascade_action = {
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.handler = k2u3_action,
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.flags = 0,
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.mask = CPU_MASK_NONE,
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.name = "U3->K2 Cascade",
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};
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#endif /* CONFIG_POWER4 */
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#ifdef CONFIG_XMON
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static struct irqaction xmon_action = {
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.handler = xmon_irq,
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.flags = 0,
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.mask = CPU_MASK_NONE,
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.name = "NMI - XMON"
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};
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#endif
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static struct irqaction gatwick_cascade_action = {
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.handler = gatwick_action,
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.flags = SA_INTERRUPT,
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.mask = CPU_MASK_NONE,
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.name = "cascade",
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};
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void __init pmac_pic_init(void)
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{
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int i;
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struct device_node *irqctrler = NULL;
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struct device_node *irqctrler2 = NULL;
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struct device_node *np;
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unsigned long addr;
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int irq_cascade = -1;
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/* We first try to detect Apple's new Core99 chipset, since mac-io
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* is quite different on those machines and contains an IBM MPIC2.
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*/
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np = find_type_devices("open-pic");
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while(np) {
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if (np->parent && !strcmp(np->parent->name, "u3"))
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irqctrler2 = np;
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else
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irqctrler = np;
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np = np->next;
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}
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if (irqctrler != NULL)
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{
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if (irqctrler->n_addrs > 0)
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{
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unsigned char senses[128];
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printk(KERN_INFO "PowerMac using OpenPIC irq controller at 0x%08x\n",
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irqctrler->addrs[0].address);
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prom_get_irq_senses(senses, 0, 128);
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OpenPIC_InitSenses = senses;
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OpenPIC_NumInitSenses = 128;
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ppc_md.get_irq = openpic_get_irq;
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pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler, 0, 0);
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OpenPIC_Addr = ioremap(irqctrler->addrs[0].address,
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irqctrler->addrs[0].size);
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openpic_init(0);
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#ifdef CONFIG_POWER4
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if (irqctrler2 != NULL && irqctrler2->n_intrs > 0 &&
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irqctrler2->n_addrs > 0) {
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printk(KERN_INFO "Slave OpenPIC at 0x%08x hooked on IRQ %d\n",
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irqctrler2->addrs[0].address,
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irqctrler2->intrs[0].line);
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pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler2, 0, 0);
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OpenPIC2_Addr = ioremap(irqctrler2->addrs[0].address,
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irqctrler2->addrs[0].size);
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prom_get_irq_senses(senses, PMAC_OPENPIC2_OFFSET,
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PMAC_OPENPIC2_OFFSET+128);
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OpenPIC_InitSenses = senses;
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OpenPIC_NumInitSenses = 128;
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openpic2_init(PMAC_OPENPIC2_OFFSET);
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if (setup_irq(irqctrler2->intrs[0].line,
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&k2u3_cascade_action))
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printk("Unable to get OpenPIC IRQ for cascade\n");
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}
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#endif /* CONFIG_POWER4 */
|
|
|
|
#ifdef CONFIG_XMON
|
|
{
|
|
struct device_node* pswitch;
|
|
int nmi_irq;
|
|
|
|
pswitch = find_devices("programmer-switch");
|
|
if (pswitch && pswitch->n_intrs) {
|
|
nmi_irq = pswitch->intrs[0].line;
|
|
openpic_init_nmi_irq(nmi_irq);
|
|
setup_irq(nmi_irq, &xmon_action);
|
|
}
|
|
}
|
|
#endif /* CONFIG_XMON */
|
|
return;
|
|
}
|
|
irqctrler = NULL;
|
|
}
|
|
|
|
/* Get the level/edge settings, assume if it's not
|
|
* a Grand Central nor an OHare, then it's an Heathrow
|
|
* (or Paddington).
|
|
*/
|
|
if (find_devices("gc"))
|
|
level_mask[0] = GC_LEVEL_MASK;
|
|
else if (find_devices("ohare")) {
|
|
level_mask[0] = OHARE_LEVEL_MASK;
|
|
/* We might have a second cascaded ohare */
|
|
level_mask[1] = OHARE_LEVEL_MASK;
|
|
} else {
|
|
level_mask[0] = HEATHROW_LEVEL_MASK;
|
|
level_mask[1] = 0;
|
|
/* We might have a second cascaded heathrow */
|
|
level_mask[2] = HEATHROW_LEVEL_MASK;
|
|
level_mask[3] = 0;
|
|
}
|
|
|
|
/*
|
|
* G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
|
|
* 1998 G3 Series PowerBooks have 128,
|
|
* other powermacs have 32.
|
|
* The combo ethernet/modem card for the Powerstar powerbooks
|
|
* (2400/3400/3500, ohare based) has a second ohare chip
|
|
* effectively making a total of 64.
|
|
*/
|
|
max_irqs = max_real_irqs = 32;
|
|
irqctrler = find_devices("mac-io");
|
|
if (irqctrler)
|
|
{
|
|
max_real_irqs = 64;
|
|
if (irqctrler->next)
|
|
max_irqs = 128;
|
|
else
|
|
max_irqs = 64;
|
|
}
|
|
for ( i = 0; i < max_real_irqs ; i++ )
|
|
irq_desc[i].handler = &pmac_pic;
|
|
|
|
/* get addresses of first controller */
|
|
if (irqctrler) {
|
|
if (irqctrler->n_addrs > 0) {
|
|
addr = (unsigned long)
|
|
ioremap(irqctrler->addrs[0].address, 0x40);
|
|
for (i = 0; i < 2; ++i)
|
|
pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
|
|
(addr + (2 - i) * 0x10);
|
|
}
|
|
|
|
/* get addresses of second controller */
|
|
irqctrler = irqctrler->next;
|
|
if (irqctrler && irqctrler->n_addrs > 0) {
|
|
addr = (unsigned long)
|
|
ioremap(irqctrler->addrs[0].address, 0x40);
|
|
for (i = 2; i < 4; ++i)
|
|
pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
|
|
(addr + (4 - i) * 0x10);
|
|
irq_cascade = irqctrler->intrs[0].line;
|
|
if (device_is_compatible(irqctrler, "gatwick"))
|
|
pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs);
|
|
}
|
|
} else {
|
|
/* older powermacs have a GC (grand central) or ohare at
|
|
f3000000, with interrupt control registers at f3000020. */
|
|
addr = (unsigned long) ioremap(0xf3000000, 0x40);
|
|
pmac_irq_hw[0] = (volatile struct pmac_irq_hw *) (addr + 0x20);
|
|
}
|
|
|
|
/* PowerBooks 3400 and 3500 can have a second controller in a second
|
|
ohare chip, on the combo ethernet/modem card */
|
|
if (machine_is_compatible("AAPL,3400/2400")
|
|
|| machine_is_compatible("AAPL,3500"))
|
|
irq_cascade = enable_second_ohare();
|
|
|
|
/* disable all interrupts in all controllers */
|
|
for (i = 0; i * 32 < max_irqs; ++i)
|
|
out_le32(&pmac_irq_hw[i]->enable, 0);
|
|
/* mark level interrupts */
|
|
for (i = 0; i < max_irqs; i++)
|
|
if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
|
|
irq_desc[i].status = IRQ_LEVEL;
|
|
|
|
/* get interrupt line of secondary interrupt controller */
|
|
if (irq_cascade >= 0) {
|
|
printk(KERN_INFO "irq: secondary controller on irq %d\n",
|
|
(int)irq_cascade);
|
|
for ( i = max_real_irqs ; i < max_irqs ; i++ )
|
|
irq_desc[i].handler = &gatwick_pic;
|
|
setup_irq(irq_cascade, &gatwick_cascade_action);
|
|
}
|
|
printk("System has %d possible interrupts\n", max_irqs);
|
|
if (max_irqs != max_real_irqs)
|
|
printk(KERN_DEBUG "%d interrupts on main controller\n",
|
|
max_real_irqs);
|
|
|
|
#ifdef CONFIG_XMON
|
|
setup_irq(20, &xmon_action);
|
|
#endif /* CONFIG_XMON */
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
/*
|
|
* These procedures are used in implementing sleep on the powerbooks.
|
|
* sleep_save_intrs() saves the states of all interrupt enables
|
|
* and disables all interrupts except for the nominated one.
|
|
* sleep_restore_intrs() restores the states of all interrupt enables.
|
|
*/
|
|
unsigned long sleep_save_mask[2];
|
|
|
|
/* This used to be passed by the PMU driver but that link got
|
|
* broken with the new driver model. We use this tweak for now...
|
|
*/
|
|
static int pmacpic_find_viaint(void)
|
|
{
|
|
int viaint = -1;
|
|
|
|
#ifdef CONFIG_ADB_PMU
|
|
struct device_node *np;
|
|
|
|
if (pmu_get_model() != PMU_OHARE_BASED)
|
|
goto not_found;
|
|
np = of_find_node_by_name(NULL, "via-pmu");
|
|
if (np == NULL)
|
|
goto not_found;
|
|
viaint = np->intrs[0].line;
|
|
#endif /* CONFIG_ADB_PMU */
|
|
|
|
not_found:
|
|
return viaint;
|
|
}
|
|
|
|
static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state)
|
|
{
|
|
int viaint = pmacpic_find_viaint();
|
|
|
|
sleep_save_mask[0] = ppc_cached_irq_mask[0];
|
|
sleep_save_mask[1] = ppc_cached_irq_mask[1];
|
|
ppc_cached_irq_mask[0] = 0;
|
|
ppc_cached_irq_mask[1] = 0;
|
|
if (viaint > 0)
|
|
set_bit(viaint, ppc_cached_irq_mask);
|
|
out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
|
|
if (max_real_irqs > 32)
|
|
out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
|
|
(void)in_le32(&pmac_irq_hw[0]->event);
|
|
/* make sure mask gets to controller before we return to caller */
|
|
mb();
|
|
(void)in_le32(&pmac_irq_hw[0]->enable);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pmacpic_resume(struct sys_device *sysdev)
|
|
{
|
|
int i;
|
|
|
|
out_le32(&pmac_irq_hw[0]->enable, 0);
|
|
if (max_real_irqs > 32)
|
|
out_le32(&pmac_irq_hw[1]->enable, 0);
|
|
mb();
|
|
for (i = 0; i < max_real_irqs; ++i)
|
|
if (test_bit(i, sleep_save_mask))
|
|
pmac_unmask_irq(i);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
static struct sysdev_class pmacpic_sysclass = {
|
|
set_kset_name("pmac_pic"),
|
|
};
|
|
|
|
static struct sys_device device_pmacpic = {
|
|
.id = 0,
|
|
.cls = &pmacpic_sysclass,
|
|
};
|
|
|
|
static struct sysdev_driver driver_pmacpic = {
|
|
#ifdef CONFIG_PM
|
|
.suspend = &pmacpic_suspend,
|
|
.resume = &pmacpic_resume,
|
|
#endif /* CONFIG_PM */
|
|
};
|
|
|
|
static int __init init_pmacpic_sysfs(void)
|
|
{
|
|
if (max_irqs == 0)
|
|
return -ENODEV;
|
|
|
|
printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
|
|
sysdev_class_register(&pmacpic_sysclass);
|
|
sysdev_register(&device_pmacpic);
|
|
sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
|
|
return 0;
|
|
}
|
|
|
|
subsys_initcall(init_pmacpic_sysfs);
|
|
|