502 lines
12 KiB
C
502 lines
12 KiB
C
/*
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* Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
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*/
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#ifndef _ASM_POWERPC_PPC_ASM_H
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#define _ASM_POWERPC_PPC_ASM_H
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#include <linux/stringify.h>
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#include <linux/config.h>
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#ifdef __ASSEMBLY__
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/*
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* Macros for storing registers into and loading registers from
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* exception frames.
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*/
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#ifdef __powerpc64__
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#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
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#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
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#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
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#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
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#else
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#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
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#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
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#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
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SAVE_10GPRS(22, base)
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#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
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REST_10GPRS(22, base)
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#endif
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#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
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#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
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#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
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#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
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#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
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#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
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#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
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#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
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#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
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#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
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#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
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#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
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#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
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#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
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#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
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#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
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#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
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#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
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#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
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#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
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#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
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#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
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#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
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#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
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#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
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#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
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#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
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#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
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#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
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#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
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#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
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#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
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#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
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#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
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#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
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#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
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#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
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#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
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#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
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#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
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#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
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#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
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#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
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#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
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/* Macros to adjust thread priority for Iseries hardware multithreading */
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#define HMT_VERY_LOW or 31,31,31 # very low priority\n"
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#define HMT_LOW or 1,1,1
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#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority\n"
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#define HMT_MEDIUM or 2,2,2
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#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority\n"
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#define HMT_HIGH or 3,3,3
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/* handle instructions that older assemblers may not know */
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#define RFCI .long 0x4c000066 /* rfci instruction */
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#define RFDI .long 0x4c00004e /* rfdi instruction */
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#define RFMCI .long 0x4c00004c /* rfmci instruction */
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#ifdef CONFIG_PPC64
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#define XGLUE(a,b) a##b
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#define GLUE(a,b) XGLUE(a,b)
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#define _GLOBAL(name) \
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.section ".text"; \
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.align 2 ; \
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.globl name; \
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.globl GLUE(.,name); \
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.section ".opd","aw"; \
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name: \
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.quad GLUE(.,name); \
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.quad .TOC.@tocbase; \
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.quad 0; \
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.previous; \
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.type GLUE(.,name),@function; \
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GLUE(.,name):
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#define _KPROBE(name) \
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.section ".kprobes.text","a"; \
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.align 2 ; \
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.globl name; \
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.globl GLUE(.,name); \
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.section ".opd","aw"; \
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name: \
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.quad GLUE(.,name); \
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.quad .TOC.@tocbase; \
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.quad 0; \
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.previous; \
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.type GLUE(.,name),@function; \
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GLUE(.,name):
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#define _STATIC(name) \
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.section ".text"; \
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.align 2 ; \
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.section ".opd","aw"; \
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name: \
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.quad GLUE(.,name); \
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.quad .TOC.@tocbase; \
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.quad 0; \
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.previous; \
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.type GLUE(.,name),@function; \
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GLUE(.,name):
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#else /* 32-bit */
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#define _GLOBAL(n) \
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.text; \
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.stabs __stringify(n:F-1),N_FUN,0,0,n;\
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.globl n; \
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n:
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#define _KPROBE(n) \
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.section ".kprobes.text","a"; \
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.globl n; \
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n:
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#endif
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/*
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* LOADADDR( rn, name )
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* loads the address of 'name' into 'rn'
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*
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* LOADBASE( rn, name )
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* loads the address (less the low 16 bits) of 'name' into 'rn'
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* suitable for base+disp addressing
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*/
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#ifdef __powerpc64__
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#define LOADADDR(rn,name) \
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lis rn,name##@highest; \
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ori rn,rn,name##@higher; \
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rldicr rn,rn,32,31; \
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oris rn,rn,name##@h; \
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ori rn,rn,name##@l
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#define LOADBASE(rn,name) \
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.section .toc,"aw"; \
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1: .tc name[TC],name; \
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.previous; \
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ld rn,1b@toc(r2)
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#define OFF(name) 0
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#define SET_REG_TO_CONST(reg, value) \
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lis reg,(((value)>>48)&0xFFFF); \
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ori reg,reg,(((value)>>32)&0xFFFF); \
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rldicr reg,reg,32,31; \
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oris reg,reg,(((value)>>16)&0xFFFF); \
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ori reg,reg,((value)&0xFFFF);
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#define SET_REG_TO_LABEL(reg, label) \
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lis reg,(label)@highest; \
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ori reg,reg,(label)@higher; \
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rldicr reg,reg,32,31; \
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oris reg,reg,(label)@h; \
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ori reg,reg,(label)@l;
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/* operations for longs and pointers */
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#define LDL ld
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#define STL std
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#define CMPI cmpdi
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#else /* 32-bit */
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#define LOADADDR(rn,name) \
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lis rn,name@ha; \
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addi rn,rn,name@l
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#define LOADBASE(rn,name) \
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lis rn,name@ha
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#define OFF(name) name@l
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/* operations for longs and pointers */
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#define LDL lwz
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#define STL stw
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#define CMPI cmpwi
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#endif
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/* various errata or part fixups */
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#ifdef CONFIG_PPC601_SYNC_FIX
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#define SYNC \
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BEGIN_FTR_SECTION \
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sync; \
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isync; \
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END_FTR_SECTION_IFSET(CPU_FTR_601)
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#define SYNC_601 \
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BEGIN_FTR_SECTION \
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sync; \
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END_FTR_SECTION_IFSET(CPU_FTR_601)
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#define ISYNC_601 \
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BEGIN_FTR_SECTION \
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isync; \
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END_FTR_SECTION_IFSET(CPU_FTR_601)
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#else
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#define SYNC
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#define SYNC_601
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#define ISYNC_601
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#endif
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#ifndef CONFIG_SMP
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#define TLBSYNC
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#else /* CONFIG_SMP */
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/* tlbsync is not implemented on 601 */
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#define TLBSYNC \
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BEGIN_FTR_SECTION \
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tlbsync; \
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sync; \
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END_FTR_SECTION_IFCLR(CPU_FTR_601)
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#endif
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/*
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* This instruction is not implemented on the PPC 603 or 601; however, on
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* the 403GCX and 405GP tlbia IS defined and tlbie is not.
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* All of these instructions exist in the 8xx, they have magical powers,
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* and they must be used.
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*/
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#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
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#define tlbia \
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li r4,1024; \
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mtctr r4; \
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lis r4,KERNELBASE@h; \
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0: tlbie r4; \
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addi r4,r4,0x1000; \
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bdnz 0b
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#endif
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#ifdef CONFIG_IBM405_ERR77
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#define PPC405_ERR77(ra,rb) dcbt ra, rb;
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#define PPC405_ERR77_SYNC sync;
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#else
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#define PPC405_ERR77(ra,rb)
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#define PPC405_ERR77_SYNC
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#endif
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#ifdef CONFIG_IBM440EP_ERR42
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#define PPC440EP_ERR42 isync
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#else
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#define PPC440EP_ERR42
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#endif
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#if defined(CONFIG_BOOKE)
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#define tophys(rd,rs) \
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addis rd,rs,0
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#define tovirt(rd,rs) \
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addis rd,rs,0
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#elif defined(CONFIG_PPC64)
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/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
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* Then we can easily do this with one asm insn. -Peter
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*/
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#define tophys(rd,rs) \
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lis rd,((KERNELBASE>>48)&0xFFFF); \
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rldicr rd,rd,32,31; \
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sub rd,rs,rd
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#define tovirt(rd,rs) \
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lis rd,((KERNELBASE>>48)&0xFFFF); \
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rldicr rd,rd,32,31; \
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add rd,rs,rd
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#else
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/*
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* On APUS (Amiga PowerPC cpu upgrade board), we don't know the
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* physical base address of RAM at compile time.
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*/
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#define tophys(rd,rs) \
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0: addis rd,rs,-KERNELBASE@h; \
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.section ".vtop_fixup","aw"; \
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.align 1; \
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.long 0b; \
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.previous
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#define tovirt(rd,rs) \
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0: addis rd,rs,KERNELBASE@h; \
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.section ".ptov_fixup","aw"; \
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.align 1; \
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.long 0b; \
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.previous
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#endif
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#ifdef CONFIG_PPC64
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#define RFI rfid
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#define MTMSRD(r) mtmsrd r
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#else
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#define FIX_SRR1(ra, rb)
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#ifndef CONFIG_40x
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#define RFI rfi
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#else
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#define RFI rfi; b . /* Prevent prefetch past rfi */
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#endif
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#define MTMSRD(r) mtmsr r
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#define CLR_TOP32(r)
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#endif
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/* The boring bits... */
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/* Condition Register Bit Fields */
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#define cr0 0
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#define cr1 1
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#define cr2 2
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#define cr3 3
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#define cr4 4
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#define cr5 5
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#define cr6 6
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#define cr7 7
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/* General Purpose Registers (GPRs) */
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#define r0 0
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#define r1 1
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#define r2 2
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#define r3 3
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#define r4 4
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#define r5 5
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#define r6 6
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#define r7 7
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#define r8 8
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#define r9 9
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#define r10 10
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#define r11 11
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#define r12 12
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#define r13 13
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#define r14 14
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#define r15 15
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#define r16 16
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#define r17 17
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#define r18 18
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#define r19 19
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#define r20 20
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#define r21 21
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#define r22 22
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#define r23 23
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#define r24 24
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#define r25 25
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#define r26 26
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#define r27 27
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#define r28 28
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#define r29 29
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#define r30 30
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#define r31 31
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/* Floating Point Registers (FPRs) */
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#define fr0 0
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#define fr1 1
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#define fr2 2
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#define fr3 3
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#define fr4 4
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#define fr5 5
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#define fr6 6
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#define fr7 7
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#define fr8 8
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#define fr9 9
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#define fr10 10
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#define fr11 11
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#define fr12 12
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#define fr13 13
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#define fr14 14
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#define fr15 15
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#define fr16 16
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#define fr17 17
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#define fr18 18
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#define fr19 19
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#define fr20 20
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#define fr21 21
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#define fr22 22
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#define fr23 23
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#define fr24 24
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#define fr25 25
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#define fr26 26
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#define fr27 27
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#define fr28 28
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#define fr29 29
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#define fr30 30
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#define fr31 31
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/* AltiVec Registers (VPRs) */
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#define vr0 0
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#define vr1 1
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#define vr2 2
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#define vr3 3
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#define vr4 4
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#define vr5 5
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#define vr6 6
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#define vr7 7
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#define vr8 8
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#define vr9 9
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#define vr10 10
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#define vr11 11
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#define vr12 12
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#define vr13 13
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#define vr14 14
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#define vr15 15
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#define vr16 16
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#define vr17 17
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#define vr18 18
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#define vr19 19
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#define vr20 20
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#define vr21 21
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#define vr22 22
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#define vr23 23
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#define vr24 24
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#define vr25 25
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#define vr26 26
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#define vr27 27
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#define vr28 28
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#define vr29 29
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#define vr30 30
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#define vr31 31
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/* SPE Registers (EVPRs) */
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#define evr0 0
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#define evr1 1
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#define evr2 2
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#define evr3 3
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#define evr4 4
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#define evr5 5
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#define evr6 6
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#define evr7 7
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#define evr8 8
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#define evr9 9
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#define evr10 10
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#define evr11 11
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#define evr12 12
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#define evr13 13
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#define evr14 14
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#define evr15 15
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#define evr16 16
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#define evr17 17
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#define evr18 18
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#define evr19 19
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#define evr20 20
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#define evr21 21
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#define evr22 22
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#define evr23 23
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#define evr24 24
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#define evr25 25
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#define evr26 26
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#define evr27 27
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#define evr28 28
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#define evr29 29
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#define evr30 30
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#define evr31 31
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/* some stab codes */
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#define N_FUN 36
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#define N_RSYM 64
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#define N_SLINE 68
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#define N_SO 100
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#define ASM_CONST(x) x
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#else
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#define __ASM_CONST(x) x##UL
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#define ASM_CONST(x) __ASM_CONST(x)
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_PPC_ASM_H */
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