1394f03221
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
96 lines
2.7 KiB
C
96 lines
2.7 KiB
C
#ifndef _BLACKFIN_PGTABLE_H
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#define _BLACKFIN_PGTABLE_H
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#include <asm-generic/4level-fixup.h>
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#include <asm/page.h>
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#include <asm/cplb.h>
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typedef pte_t *pte_addr_t;
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/*
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* Trivial page table functions.
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*/
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#define pgd_present(pgd) (1)
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#define pgd_none(pgd) (0)
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#define pgd_bad(pgd) (0)
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#define pgd_clear(pgdp)
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#define kern_addr_valid(addr) (1)
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#define pmd_offset(a, b) ((void *)0)
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#define pmd_none(x) (!pmd_val(x))
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#define pmd_present(x) (pmd_val(x))
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#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
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#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
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#define kern_addr_valid(addr) (1)
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#define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */
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#define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */
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#define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */
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#define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */
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#define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */
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extern void paging_init(void);
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#define __swp_type(x) (0)
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#define __swp_offset(x) (0)
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#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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static inline int pte_file(pte_t pte)
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{
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return 0;
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}
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#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
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#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
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/*
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* Page assess control based on Blackfin CPLB management
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*/
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#define _PAGE_RD (CPLB_USER_RD)
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#define _PAGE_WR (CPLB_USER_WR)
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#define _PAGE_USER (CPLB_USER_RD | CPLB_USER_WR)
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#define _PAGE_ACCESSED CPLB_ALL_ACCESS
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#define _PAGE_DIRTY (CPLB_DIRTY)
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#define PTE_BIT_FUNC(fn, op) \
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static inline pte_t pte_##fn(pte_t _pte) { _pte.pte op; return _pte; }
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PTE_BIT_FUNC(rdprotect, &= ~_PAGE_RD);
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PTE_BIT_FUNC(mkread, |= _PAGE_RD);
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PTE_BIT_FUNC(wrprotect, &= ~_PAGE_WR);
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PTE_BIT_FUNC(mkwrite, |= _PAGE_WR);
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PTE_BIT_FUNC(exprotect, &= ~_PAGE_USER);
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PTE_BIT_FUNC(mkexec, |= _PAGE_USER);
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PTE_BIT_FUNC(mkclean, &= ~_PAGE_DIRTY);
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PTE_BIT_FUNC(mkdirty, |= _PAGE_DIRTY);
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PTE_BIT_FUNC(mkold, &= ~_PAGE_ACCESSED);
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PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED);
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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#define ZERO_PAGE(vaddr) (virt_to_page(0))
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extern unsigned int kobjsize(const void *objp);
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#define swapper_pg_dir ((pgd_t *) 0)
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/*
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* No page table caches to initialise.
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*/
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#define pgtable_cache_init() do { } while (0)
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#define io_remap_pfn_range remap_pfn_range
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/*
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* All 32bit addresses are effectively valid for vmalloc...
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* Sort of meaningless for non-VM targets.
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*/
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#define VMALLOC_START 0
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#define VMALLOC_END 0xffffffff
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#include <asm-generic/pgtable.h>
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#endif /* _BLACKFIN_PGTABLE_H */
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