8c2f4a8dd0
1. ./genfilelist.pl arch/arc/include/asm/
2. Create arch/arc/include/uapi/asm/Kbuild as follows
+# UAPI Header export list
+include include/uapi/asm-generic/Kbuild.asm
3. ./disintegrate-one.pl arch/arc/include/{,uapi/}asm/<above-list>
4. Edit arch/arc/include/asm/Kbuild to remove ref to
asm-generic/Kbuild.asm
- To work around empty uapi/asm/setup.h added a placholder comment.
- Also a manual #ifdef __ASSEMBLY__ for a late ptrace change
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Cc: David Howells <dhowells@redhat.com>
98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: May 2011
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* -Support single cycle endian-swap insn in ARC700 4.10
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*
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* vineetg: June 2009
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* -Better htonl implementation (5 instead of 9 ALU instructions)
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* -Hardware assisted single cycle bswap (Use Case of ARC custom instrn)
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*/
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#ifndef __ASM_ARC_SWAB_H
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#define __ASM_ARC_SWAB_H
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#include <linux/types.h>
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/* Native single cycle endian swap insn */
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#ifdef CONFIG_ARC_HAS_SWAPE
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#define __arch_swab32(x) \
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({ \
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unsigned int tmp = x; \
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__asm__( \
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" swape %0, %1 \n" \
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: "=r" (tmp) \
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: "r" (tmp)); \
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tmp; \
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})
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#else
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/* Several ways of Endian-Swap Emulation for ARC
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* 0: kernel generic
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* 1: ARC optimised "C"
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* 2: ARC Custom instruction
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*/
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#define ARC_BSWAP_TYPE 1
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#if (ARC_BSWAP_TYPE == 1) /******* Software only ********/
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/* The kernel default implementation of htonl is
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* return x<<24 | x>>24 |
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* (x & (__u32)0x0000ff00UL)<<8 | (x & (__u32)0x00ff0000UL)>>8;
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*
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* This generates 9 instructions on ARC (excluding the ld/st)
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*
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* 8051fd8c: ld r3,[r7,20] ; Mem op : Get the value to be swapped
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* 8051fd98: asl r5,r3,24 ; get 3rd Byte
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* 8051fd9c: lsr r2,r3,24 ; get 0th Byte
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* 8051fda0: and r4,r3,0xff00
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* 8051fda8: asl r4,r4,8 ; get 1st Byte
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* 8051fdac: and r3,r3,0x00ff0000
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* 8051fdb4: or r2,r2,r5 ; combine 0th and 3rd Bytes
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* 8051fdb8: lsr r3,r3,8 ; 2nd Byte at correct place in Dst Reg
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* 8051fdbc: or r2,r2,r4 ; combine 0,3 Bytes with 1st Byte
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* 8051fdc0: or r2,r2,r3 ; combine 0,3,1 Bytes with 2nd Byte
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* 8051fdc4: st r2,[r1,20] ; Mem op : save result back to mem
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*
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* Joern suggested a better "C" algorithm which is great since
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* (1) It is portable to any architecure
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* (2) At the same time it takes advantage of ARC ISA (rotate intrns)
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*/
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#define __arch_swab32(x) \
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({ unsigned long __in = (x), __tmp; \
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__tmp = __in << 8 | __in >> 24; /* ror tmp,in,24 */ \
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__in = __in << 24 | __in >> 8; /* ror in,in,8 */ \
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__tmp ^= __in; \
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__tmp &= 0xff00ff; \
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__tmp ^ __in; \
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})
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#elif (ARC_BSWAP_TYPE == 2) /* Custom single cycle bwap instruction */
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#define __arch_swab32(x) \
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({ \
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unsigned int tmp = x; \
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__asm__( \
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" .extInstruction bswap, 7, 0x00, SUFFIX_NONE, SYNTAX_2OP \n"\
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" bswap %0, %1 \n"\
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: "=r" (tmp) \
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: "r" (tmp)); \
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tmp; \
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})
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#endif /* ARC_BSWAP_TYPE=zzz */
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#endif /* CONFIG_ARC_HAS_SWAPE */
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#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
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#define __SWAB_64_THRU_32__
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#endif
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#endif
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