9f825962ef
This adds optimized memset/bzero/page-clear routines for Niagara-4. We basically can do what powerpc has been able to do for a decade (via the "dcbz" instruction), which is use cache line clearing stores for bzero and memsets with a 'c' argument of zero. As long as we make the cache initializing store to each 32-byte subblock of the L2 cache line, it works. As with other Niagara-4 optimized routines, the key is to make sure to avoid any usage of the %asi register, as reads and writes to it cost at least 50 cycles. For the user clear cases, we don't use these new routines, we use the Niagara-1 variants instead. Those have to use %asi in an unavoidable way. A Niagara-4 8K page clear costs just under 600 cycles. Add definitions of the MRU variants of the cache initializing store ASIs. By default, cache initializing stores install the line as Least Recently Used. If we know we're going to use the data immediately (which is true for page copies and clears) we can use the Most Recently Used variant, to decrease the likelyhood of the lines being evicted before they get used. Signed-off-by: David S. Miller <davem@davemloft.net>
29 lines
No EOL
642 B
ArmAsm
29 lines
No EOL
642 B
ArmAsm
/* NG4copy_page.S: Niagara-4 optimized clear page.
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*
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* Copyright (C) 2012 (davem@davemloft.net)
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*/
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#include <asm/asi.h>
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#include <asm/page.h>
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.text
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.register %g3, #scratch
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.align 32
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.globl NG4clear_page
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.globl NG4clear_user_page
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NG4clear_page: /* %o0=dest */
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NG4clear_user_page: /* %o0=dest, %o1=vaddr */
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set PAGE_SIZE, %g7
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mov 0x20, %g3
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1: stxa %g0, [%o0 + %g0] ASI_ST_BLKINIT_MRU_P
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subcc %g7, 0x40, %g7
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stxa %g0, [%o0 + %g3] ASI_ST_BLKINIT_MRU_P
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bne,pt %xcc, 1b
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add %o0, 0x40, %o0
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membar #StoreLoad|#StoreStore
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retl
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nop
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.size NG4clear_page,.-NG4clear_page
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.size NG4clear_user_page,.-NG4clear_user_page |