cbda94e039
These changes are mostly for ARM specific device drivers that either don't have an upstream maintainer, or that had the maintainer ask us to pick up the changes to avoid conflicts. A large chunk of this are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from that, reset controllers for STi as well as a large rework of the Marvell Orion/EBU watchdog driver are notable. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUz/1+GCrR//JCVInAQJmfg/9GyqHatDjjUPUBjUQRIEtKgGdmQwdbDqF x+OrS/q5B5zYbpIWkbkt1IUYJfU+89Z5ev9jxI4rV824Nu9Y92mHPDnv+N/ptkIh q2OVP3bQDpWs3aEVV2B1HBNcWrNUuwco9BJu05eegEePii/cto0/wKwWIgUmrmjy xOLthsnp2YmeplGs7ctC6Dz8XbmELebpawejTGylARXei/SwmzB/YYDgJbYjRL2I WSCVa8Vo+MZaGC/yxdKVTtvsKVQenxGoMO3ojikJeRdvuVRJds48Cw+UBdzWYNeJ 3Ssvbdx6Xltf9jy/7H0btOUgxPetZuUV+2XpbWfGu0Zr9FcGDv3q9hrxA+UYKnkY GIGU0otSsmpHnX5Ms3E2xnHiV/fihxA3qohqts5kYRBDr5uc+IpW6SbDymQliCGG OO4XmIVM3pmsqAqP3Zuseemt9CeSW2yC0XlfXkzjO74yY39c+WLBbtGI40Z5W6i0 mM1C8RD3QSNijYCEC8eqz06BQfRImsPs+jllsnJTZaHfbOsib718uvandjfG26lN 616YMcqq0Sp51HIQ4qW7f2dQr7vOyNqbukdkrwF5JgkY/nVki5kdciRg/yeipRy6 Ey80a+OTq0GQljM0F2dcH/A1eHH9KsuI1L6NdSMJsl0h6guIBORPTwTw3qJ13OkR wpJyM+Gm+Fk= =u/FI -----END PGP SIGNATURE----- Merge tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver changes from Arnd Bergmann: "These changes are mostly for ARM specific device drivers that either don't have an upstream maintainer, or that had the maintainer ask us to pick up the changes to avoid conflicts. A large chunk of this are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from that, reset controllers for STi as well as a large rework of the Marvell Orion/EBU watchdog driver are notable" * tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits) Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac." Revert "net: stmmac: Add SOCFPGA glue driver" ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks ARM: STi: Add reset controller support to mach-sti Kconfig drivers: reset: stih416: add softreset controller drivers: reset: stih415: add softreset controller drivers: reset: Reset controller driver for STiH416 drivers: reset: Reset controller driver for STiH415 drivers: reset: STi SoC system configuration reset controller support dts: socfpga: Add sysmgr node so the gmac can use to reference dts: socfpga: Add support for SD/MMC on the SOCFPGA platform reset: Add optional resets and stubs ARM: shmobile: r7s72100: fix bus clock calculation Power: Reset: Generalize qnap-poweroff to work on Synology devices. dts: socfpga: Update clock entry to support multiple parents ARM: socfpga: Update socfpga_defconfig dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. net: stmmac: Add SOCFPGA glue driver watchdog: orion_wdt: Use %pa to print 'phys_addr_t' drivers: cci: Export CCI PMU revision ...
272 lines
10 KiB
C
272 lines
10 KiB
C
/*
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* r8a7779 clock framework support
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/bitops.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/clock.h>
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#include <mach/common.h>
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/*
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* MD1 = 1 MD1 = 0
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* (PLLA = 1500) (PLLA = 1600)
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* (MHz) (MHz)
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*------------------------------------------------+--------------------
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* clkz 1000 (2/3) 800 (1/2)
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* clkzs 250 (1/6) 200 (1/8)
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* clki 750 (1/2) 800 (1/2)
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* clks 250 (1/6) 200 (1/8)
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* clks1 125 (1/12) 100 (1/16)
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* clks3 187.5 (1/8) 200 (1/8)
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* clks4 93.7 (1/16) 100 (1/16)
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* clkp 62.5 (1/24) 50 (1/32)
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* clkg 62.5 (1/24) 66.6 (1/24)
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* clkb, CLKOUT
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* (MD2 = 0) 62.5 (1/24) 66.6 (1/24)
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* (MD2 = 1) 41.6 (1/36) 50 (1/32)
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*/
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#define MD(nr) BIT(nr)
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#define MSTPCR0 IOMEM(0xffc80030)
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#define MSTPCR1 IOMEM(0xffc80034)
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#define MSTPCR3 IOMEM(0xffc8003c)
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#define MSTPSR1 IOMEM(0xffc80044)
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#define MODEMR 0xffcc0020
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/* ioremap() through clock mapping mandatory to avoid
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* collision with ARM coherent DMA virtual memory range.
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*/
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static struct clk_mapping cpg_mapping = {
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.phys = 0xffc80000,
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.len = 0x80,
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};
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/*
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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static struct clk plla_clk = {
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/* .rate will be updated on r8a7779_clock_init() */
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.mapping = &cpg_mapping,
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};
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/*
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* clock ratio of these clock will be updated
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* on r8a7779_clock_init()
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*/
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SH_FIXED_RATIO_CLK_SET(clkz_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(clkzs_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(clki_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(clks_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(clks1_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(clks3_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(clks4_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(clkb_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(clkout_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(clkp_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(clkg_clk, plla_clk, 1, 1);
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static struct clk *main_clks[] = {
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&plla_clk,
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&clkz_clk,
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&clkzs_clk,
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&clki_clk,
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&clks_clk,
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&clks1_clk,
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&clks3_clk,
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&clks4_clk,
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&clkb_clk,
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&clkout_clk,
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&clkp_clk,
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&clkg_clk,
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};
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enum { MSTP323, MSTP322, MSTP321, MSTP320,
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MSTP120,
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MSTP116, MSTP115, MSTP114,
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MSTP110, MSTP109, MSTP108,
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MSTP103, MSTP101, MSTP100,
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MSTP030,
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MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
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MSTP016, MSTP015, MSTP014,
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MSTP007,
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MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP323] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 23, 0), /* SDHI0 */
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[MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
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[MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
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[MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
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[MSTP120] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 20, MSTPSR1, 0), /* VIN3 */
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[MSTP116] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 16, MSTPSR1, 0), /* PCIe */
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[MSTP115] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 15, MSTPSR1, 0), /* SATA */
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[MSTP114] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 14, MSTPSR1, 0), /* Ether */
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[MSTP110] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 10, MSTPSR1, 0), /* VIN0 */
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[MSTP109] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 9, MSTPSR1, 0), /* VIN1 */
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[MSTP108] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 8, MSTPSR1, 0), /* VIN2 */
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[MSTP103] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 3, MSTPSR1, 0), /* DU */
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[MSTP101] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 1, MSTPSR1, 0), /* USB2 */
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[MSTP100] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 0, MSTPSR1, 0), /* USB0/1 */
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[MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */
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[MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */
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[MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */
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[MSTP027] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 27, 0), /* I2C3 */
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[MSTP026] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 26, 0), /* SCIF0 */
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[MSTP025] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 25, 0), /* SCIF1 */
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[MSTP024] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 24, 0), /* SCIF2 */
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[MSTP023] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 23, 0), /* SCIF3 */
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[MSTP022] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 22, 0), /* SCIF4 */
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[MSTP021] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 21, 0), /* SCIF5 */
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[MSTP016] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 16, 0), /* TMU0 */
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[MSTP015] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 15, 0), /* TMU1 */
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[MSTP014] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 14, 0), /* TMU2 */
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[MSTP007] = SH_CLK_MSTP32(&clks_clk, MSTPCR0, 7, 0), /* HSPI */
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};
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("plla_clk", &plla_clk),
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CLKDEV_CON_ID("clkz_clk", &clkz_clk),
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CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
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/* DIV4 clocks */
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CLKDEV_CON_ID("shyway_clk", &clks_clk),
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CLKDEV_CON_ID("bus_clk", &clkout_clk),
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CLKDEV_CON_ID("shyway4_clk", &clks4_clk),
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CLKDEV_CON_ID("shyway3_clk", &clks3_clk),
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CLKDEV_CON_ID("shyway1_clk", &clks1_clk),
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CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
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/* MSTP32 clocks */
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CLKDEV_DEV_ID("r8a7779-vin.3", &mstp_clks[MSTP120]), /* VIN3 */
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CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
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CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
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CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
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CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */
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CLKDEV_DEV_ID("r8a7779-vin.0", &mstp_clks[MSTP110]), /* VIN0 */
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CLKDEV_DEV_ID("r8a7779-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
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CLKDEV_DEV_ID("r8a7779-vin.2", &mstp_clks[MSTP108]), /* VIN2 */
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CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
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CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
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CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
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CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
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CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
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CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
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CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */
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CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
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CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
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CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
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CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
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CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
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CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
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CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
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CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
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CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
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CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
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CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
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CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
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CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
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CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
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CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
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CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
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CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
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CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
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CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
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CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
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CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */
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CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
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CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */
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CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
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CLKDEV_DEV_ID("ffe4e000.sd", &mstp_clks[MSTP321]), /* SDHI2 */
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CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
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CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP320]), /* SDHI3 */
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CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */
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};
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void __init r8a7779_clock_init(void)
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{
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void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
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u32 mode;
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int k, ret = 0;
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BUG_ON(!modemr);
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mode = ioread32(modemr);
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iounmap(modemr);
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if (mode & MD(1)) {
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plla_clk.rate = 1500000000;
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SH_CLK_SET_RATIO(&clkz_clk_ratio, 2, 3);
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SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 6);
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SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
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SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 6);
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SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 12);
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SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
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SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
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SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 24);
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SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
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if (mode & MD(2)) {
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SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 36);
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SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 36);
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} else {
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SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
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SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
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}
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} else {
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plla_clk.rate = 1600000000;
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SH_CLK_SET_RATIO(&clkz_clk_ratio, 1, 2);
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SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 8);
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SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
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SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 8);
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SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 16);
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SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
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SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
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SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 32);
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SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
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if (mode & MD(2)) {
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SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 32);
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SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 32);
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} else {
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SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
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SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
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}
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}
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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shmobile_clk_init();
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else
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panic("failed to setup r8a7779 clocks\n");
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}
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