397d77a566
- some updates on the defconfig front - two SoCs converted to Device Tree: sam9261 and sam9rl (with use of CCF!) - a little PWM clock update that goes on top of this -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJTIJ7GAAoJEAf03oE53VmQ3xgIAMtWSo91ENlnr38ZtEN+J71j lrUdI/0sfv4pY2Dw0VbrnFS4hNmvM25C4dIR7SxU3iOnIC0vzzkPqs2hdRHwUY6y pw9NsnF3kW950vf/M6nDmHxQpwKZOCpABs5EDjO6S4Ky6sze4IPog+vb5Y7ovGCl LSqL9col3RCHIGyBWq77T3/NbWKOrz67Fy3eqJRyio7H8zYaEGnIrm2jPXYwtToT /FB9sZUunjYwdTRdGNhRiTHWktwlr4i4f8woHTZg85MGKY6DOsZgxzUvCXdGBeJx XaQ70hE8BF78Lglx8WUBgxowxJ1FvehxxcfzoYAVafwMlik+tSd3l0Zq3Sf6xD8= =Q3FC -----END PGP SIGNATURE----- Merge tag 'at91-cleanup' of git://github.com/at91linux/linux-at91 into next/cleanup Merge "First batch of AT91 cleanup for 3.15" from Nicolas Ferre: - some updates on the defconfig front - two SoCs converted to Device Tree: sam9261 and sam9rl (with use of CCF!) - a little PWM clock update that goes on top of this * tag 'at91-cleanup' of git://github.com/at91linux/linux-at91: ARM: at91: add PWM clock ARM: at91: move sam9261 SoC to common clk ARM: at91: prepare common clk transition for sam9261 SoC ARM: at91: updated the at91_dt_defconfig with support for the ADS7846 ARM: at91: dt: sam9261: Device Tree support for the at91sam9261ek ARM: at91: dt: defconfig: Added the sam9261 to the list of DT-enabled SOCs ARM: at91: dt: Add at91sam9261 dt SoC support ARM: at91: switch sam9rl to common clock framework ARM: at91/dt: define main clk frequency of at91sam9rlek ARM: at91/dt: define at91sam9rl clocks ARM: at91: prepare common clk transition for sam9rl SoCs ARM: at91: prepare sam9 dt boards transition to common clk ARM: at91: dt: sam9rl: Device Tree for the at91sam9rlek ARM: at91/defconfig: Add the sam9rl to the list of DT-enabled SOCs ARM: at91: Add at91sam9rl DT SoC support ARM: at91: prepare at91sam9rl DT transition ARM: at91/defconfig: refresh at91sam9260_9g20_defconfig ARM: at91/defconfig: remove useless configuration in at91sam9260_9g20_defconfig ARM: at91/defconfig: refresh at91sam9rl_defconfig Signed-off-by: Arnd Bergmann <arnd@arndb.de>
374 lines
10 KiB
C
374 lines
10 KiB
C
/*
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* arch/arm/mach-at91/at91sam9261.c
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*
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* Copyright (C) 2005 SAN People
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <linux/clk/at91_pmc.h>
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#include <asm/proc-fns.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/system_misc.h>
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#include <mach/cpu.h>
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#include <mach/at91sam9261.h>
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#include <mach/hardware.h>
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#include "at91_aic.h"
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#include "at91_rstc.h"
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#include "soc.h"
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#include "generic.h"
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#include "sam9_smc.h"
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#include "pm.h"
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#if defined(CONFIG_OLD_CLK_AT91)
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#include "clock.h"
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioA_clk = {
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.name = "pioA_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_PIOA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioB_clk = {
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.name = "pioB_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_PIOB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioC_clk = {
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.name = "pioC_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_PIOC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_US0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_US1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_US2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc_clk = {
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.name = "mci_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_MCI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udc_clk = {
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.name = "udc_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_UDP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi_clk = {
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.name = "twi_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_TWI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi0_clk = {
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.name = "spi0_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_SPI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi1_clk = {
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.name = "spi1_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_SPI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc0_clk = {
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.name = "ssc0_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_SSC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc1_clk = {
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.name = "ssc1_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_SSC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc2_clk = {
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.name = "ssc2_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_SSC2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc0_clk = {
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.name = "tc0_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_TC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc1_clk = {
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.name = "tc1_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_TC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc2_clk = {
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.name = "tc2_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_TC2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ohci_clk = {
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.name = "ohci_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_UHP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.pmc_mask = 1 << AT91SAM9261_ID_LCDC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* HClocks */
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static struct clk hck0 = {
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.name = "hck0",
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.pmc_mask = AT91_PMC_HCK0,
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.type = CLK_TYPE_SYSTEM,
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.id = 0,
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};
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static struct clk hck1 = {
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.name = "hck1",
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.pmc_mask = AT91_PMC_HCK1,
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.type = CLK_TYPE_SYSTEM,
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.id = 1,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioB_clk,
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&pioC_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&mmc_clk,
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&udc_clk,
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&twi_clk,
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&spi0_clk,
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&spi1_clk,
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&ssc0_clk,
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&ssc1_clk,
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&ssc2_clk,
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&tc0_clk,
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&tc1_clk,
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&tc2_clk,
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&ohci_clk,
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&lcdc_clk,
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// irq0 .. irq2
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};
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static struct clk_lookup periph_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
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CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
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CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
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CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
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CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
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CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
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CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
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CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
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CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
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CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
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CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
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CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
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CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
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CLKDEV_CON_ID("pioA", &pioA_clk),
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CLKDEV_CON_ID("pioB", &pioB_clk),
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CLKDEV_CON_ID("pioC", &pioC_clk),
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/* more lookup table for DT entries */
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CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
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CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
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CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
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CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
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CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &hck0),
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CLKDEV_CON_DEV_ID("hclk", "600000.fb", &hck1),
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CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
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CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
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};
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static struct clk_lookup usart_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
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};
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/*
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* The four programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static struct clk pck2 = {
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.name = "pck2",
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.pmc_mask = AT91_PMC_PCK2,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 2,
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};
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static struct clk pck3 = {
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.name = "pck3",
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.pmc_mask = AT91_PMC_PCK3,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 3,
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};
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static void __init at91sam9261_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clkdev_add_table(periph_clocks_lookups,
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ARRAY_SIZE(periph_clocks_lookups));
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clkdev_add_table(usart_clocks_lookups,
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ARRAY_SIZE(usart_clocks_lookups));
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clk_register(&pck0);
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clk_register(&pck1);
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clk_register(&pck2);
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clk_register(&pck3);
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clk_register(&hck0);
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clk_register(&hck1);
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}
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#else
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#define at91sam9261_register_clocks NULL
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#endif
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/* --------------------------------------------------------------------
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* GPIO
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* -------------------------------------------------------------------- */
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static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
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{
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.id = AT91SAM9261_ID_PIOA,
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.regbase = AT91SAM9261_BASE_PIOA,
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}, {
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.id = AT91SAM9261_ID_PIOB,
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.regbase = AT91SAM9261_BASE_PIOB,
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}, {
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.id = AT91SAM9261_ID_PIOC,
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.regbase = AT91SAM9261_BASE_PIOC,
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}
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};
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/* --------------------------------------------------------------------
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* AT91SAM9261 processor initialization
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* -------------------------------------------------------------------- */
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static void __init at91sam9261_map_io(void)
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{
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if (cpu_is_at91sam9g10())
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at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
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else
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at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
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}
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static void __init at91sam9261_ioremap_registers(void)
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{
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at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
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at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
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at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
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at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
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at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
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at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
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at91_pm_set_standby(at91sam9_sdram_standby);
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}
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static void __init at91sam9261_initialize(void)
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{
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arm_pm_idle = at91sam9_idle;
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arm_pm_restart = at91sam9_alt_restart;
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at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9261_gpio, 3);
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}
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
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7, /* Advanced Interrupt Controller */
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7, /* System Peripherals */
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1, /* Parallel IO Controller A */
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1, /* Parallel IO Controller B */
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1, /* Parallel IO Controller C */
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0,
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5, /* USART 0 */
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5, /* USART 1 */
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5, /* USART 2 */
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0, /* Multimedia Card Interface */
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2, /* USB Device Port */
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6, /* Two-Wire Interface */
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5, /* Serial Peripheral Interface 0 */
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5, /* Serial Peripheral Interface 1 */
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4, /* Serial Synchronous Controller 0 */
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4, /* Serial Synchronous Controller 1 */
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4, /* Serial Synchronous Controller 2 */
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0, /* Timer Counter 0 */
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0, /* Timer Counter 1 */
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0, /* Timer Counter 2 */
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2, /* USB Host port */
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3, /* LCD Controller */
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0, /* Advanced Interrupt Controller */
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0, /* Advanced Interrupt Controller */
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0, /* Advanced Interrupt Controller */
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};
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AT91_SOC_START(at91sam9261)
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.map_io = at91sam9261_map_io,
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.default_irq_priority = at91sam9261_default_irq_priority,
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.extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
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| (1 << AT91SAM9261_ID_IRQ2),
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.ioremap_registers = at91sam9261_ioremap_registers,
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.register_clocks = at91sam9261_register_clocks,
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.init = at91sam9261_initialize,
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AT91_SOC_END
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