11d73c56b9
ARCH_MULTIPLATFORM. (For multi-platform code it's already unused since387798b(ARM: initial multiplatform support).) To make this work some code out of arch/arm needed to be adapted. The respective changes got acks by their maintainers to be taken via armsoc (with Andrew Morton substituting for Alessandro Zummo as rtc maintainer). Compared to the previous pull request there was another patch added that fixes a (non-critical) regression on ixp4xx. Olof Johansson asked to not squash this fix into the original commit to save him from the need to reverify the series. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABCAAGBQJTA8PeAAoJEOLc3ZEyZpvW5GEP/iz+HIx8Rkf3exUOorZB0Kef dPC1Bmc4SThffhgmmXTjSapTzjfnuC8xq8dni008L7QR0LFJsC/rw8bR9GqYhTDs EP7Sk0vDJcTUw9dvlIG0jpBioxdsPY7isU8K85tr2a+dzi4JA2h8iv6gE7bsOf1c b18hIWp2ZZdeYQX3OcuzPeVfvXuMaayBJChq0akoW7zqxG2nHG9j1vCSOhBtrgpc xCTuEqPoaDOdXjdhyda//3SKkIYh1eMf+RWMgW38vz2uHEI3AsMn/EWe6pNRKzRt JdVC6LWFl5tl1Dz73NoGFQO+ztTBb2pTrmqggc+Hi4iTekJSmJSFU51D/E0hdJFj KmWDWPLiUdAItjPuRz/HyeZxoIZQjg9PJ8MkjwVNAz4f4Vmw2xNnAV1Eur3k9JyV fo55eaBvy2KIGzBB+/ksMUvs4HzMJ7Z/dVPzZYRF8VxlYFJXExT0O42oeJ8KsfH7 dJ1bjk+3VIWPLH3DHyyiIfBL1oxe4MemqrAREFnN2QxYHyCipXLwH35uNZXAqvcU jverroWnCdrpOn9KI+vpnp/kuE7Qc1IH/AwAZngPj2xhaFapiH6h1JK/xWcWjijR AKv1DhFJMqSp9fvclr/ZAb7o35V/LG0rpCs+oZumCCARwpxkbo8xXgG0CfPsYFrG KwLWPz5zwySGwvDZ2wub =g6PN -----END PGP SIGNATURE----- Merge tag 'dropmachtimexh-v2' of git://git.pengutronix.de/git/ukl/linux into next/cleanup This cleanup series gets rid of <mach/timex.h> for platforms not using ARCH_MULTIPLATFORM. (For multi-platform code it's already unused since387798b(ARM: initial multiplatform support).) To make this work some code out of arch/arm needed to be adapted. The respective changes got acks by their maintainers to be taken via armsoc (with Andrew Morton substituting for Alessandro Zummo as rtc maintainer). Compared to the previous pull request there was another patch added that fixes a (non-critical) regression on ixp4xx. Olof Johansson asked to not squash this fix into the original commit to save him from the need to reverify the series. * tag 'dropmachtimexh-v2' of git://git.pengutronix.de/git/ukl/linux: ARM: ixp4xx: fix timer latch calculation ARM: drop <mach/timex.h> for !ARCH_MULTIPLATFORM, too ARM: rpc: stop using <mach/timex.h> ARM: ixp4xx: stop using <mach/timex.h> input: ixp4xx-beeper: don't use symbols from <mach/timex.h> ARM: at91: don't use <mach/timex.h> ARM: ep93xx: stop using mach/timex.h ARM: mmp: stop using mach/timex.h ARM: netx: stop using mach/timex.h ARM: sa1100: stop using mach/timex.h clocksource: sirf/marco+prima2: drop usage of CLOCK_TICK_RATE rtc: pxa: drop unused #define TIMER_FREQ rtc: at91sam9: include <mach/hardware.h> explicitly ARM/serial: at91: switch atmel serial to use gpiolib Signed-off-by: Olof Johansson <olof@lixom.net>
411 lines
11 KiB
C
411 lines
11 KiB
C
/*
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* arch/arm/mach-at91/at91sam9260.c
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*
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* Copyright (C) 2006 SAN People
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <linux/clk/at91_pmc.h>
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#include <asm/proc-fns.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/system_misc.h>
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#include <mach/cpu.h>
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#include <mach/at91_dbgu.h>
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#include <mach/at91sam9260.h>
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#include <mach/hardware.h>
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#include "at91_aic.h"
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#include "at91_rstc.h"
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#include "soc.h"
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#include "generic.h"
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#include "clock.h"
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#include "sam9_smc.h"
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#include "pm.h"
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioA_clk = {
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.name = "pioA_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_PIOA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioB_clk = {
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.name = "pioB_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_PIOB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioC_clk = {
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.name = "pioC_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_PIOC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk adc_clk = {
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.name = "adc_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_ADC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk adc_op_clk = {
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.name = "adc_op_clk",
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.type = CLK_TYPE_PERIPHERAL,
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.rate_hz = 5000000,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc_clk = {
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.name = "mci_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_MCI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udc_clk = {
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.name = "udc_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_UDP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi_clk = {
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.name = "twi_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TWI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi0_clk = {
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.name = "spi0_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_SPI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi1_clk = {
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.name = "spi1_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_SPI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc_clk = {
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.name = "ssc_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_SSC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc0_clk = {
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.name = "tc0_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc1_clk = {
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.name = "tc1_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc2_clk = {
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.name = "tc2_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ohci_clk = {
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.name = "ohci_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_UHP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk macb_clk = {
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.name = "pclk",
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.pmc_mask = 1 << AT91SAM9260_ID_EMAC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk isi_clk = {
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.name = "isi_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_ISI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart3_clk = {
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.name = "usart3_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart4_clk = {
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.name = "usart4_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US4,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart5_clk = {
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.name = "usart5_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US5,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc3_clk = {
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.name = "tc3_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc4_clk = {
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.name = "tc4_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC4,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc5_clk = {
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.name = "tc5_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC5,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioB_clk,
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&pioC_clk,
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&adc_clk,
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&adc_op_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&mmc_clk,
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&udc_clk,
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&twi_clk,
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&spi0_clk,
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&spi1_clk,
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&ssc_clk,
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&tc0_clk,
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&tc1_clk,
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&tc2_clk,
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&ohci_clk,
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&macb_clk,
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&isi_clk,
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&usart3_clk,
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&usart4_clk,
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&usart5_clk,
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&tc3_clk,
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&tc4_clk,
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&tc5_clk,
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// irq0 .. irq2
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};
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static struct clk_lookup periph_clocks_lookups[] = {
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/* One additional fake clock for macb_hclk */
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CLKDEV_CON_ID("hclk", &macb_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
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CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
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CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
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CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
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CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
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CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
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CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
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CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
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CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
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/* more usart lookup table for DT entries */
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CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
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CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
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CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
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CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
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/* more tc lookup table for DT entries */
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CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
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CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
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CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
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CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
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CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
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CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
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CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
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/* fake hclk clock */
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CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
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CLKDEV_CON_ID("pioA", &pioA_clk),
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CLKDEV_CON_ID("pioB", &pioB_clk),
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CLKDEV_CON_ID("pioC", &pioC_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
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};
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static struct clk_lookup usart_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
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};
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/*
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* The two programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static void __init at91sam9260_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clkdev_add_table(periph_clocks_lookups,
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ARRAY_SIZE(periph_clocks_lookups));
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clkdev_add_table(usart_clocks_lookups,
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ARRAY_SIZE(usart_clocks_lookups));
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clk_register(&pck0);
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clk_register(&pck1);
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}
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/* --------------------------------------------------------------------
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* GPIO
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* -------------------------------------------------------------------- */
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static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
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{
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.id = AT91SAM9260_ID_PIOA,
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.regbase = AT91SAM9260_BASE_PIOA,
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}, {
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.id = AT91SAM9260_ID_PIOB,
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.regbase = AT91SAM9260_BASE_PIOB,
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}, {
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.id = AT91SAM9260_ID_PIOC,
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.regbase = AT91SAM9260_BASE_PIOC,
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}
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};
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/* --------------------------------------------------------------------
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* AT91SAM9260 processor initialization
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* -------------------------------------------------------------------- */
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static void __init at91sam9xe_map_io(void)
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{
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unsigned long sram_size;
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switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
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case AT91_CIDR_SRAMSIZ_32K:
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sram_size = 2 * SZ_16K;
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break;
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case AT91_CIDR_SRAMSIZ_16K:
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default:
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sram_size = SZ_16K;
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}
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at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
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}
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static void __init at91sam9260_map_io(void)
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{
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if (cpu_is_at91sam9xe())
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at91sam9xe_map_io();
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else if (cpu_is_at91sam9g20())
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at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
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else
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at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
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}
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static void __init at91sam9260_ioremap_registers(void)
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{
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at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
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at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
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at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
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at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
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at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
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at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
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at91_pm_set_standby(at91sam9_sdram_standby);
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}
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static void __init at91sam9260_initialize(void)
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{
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arm_pm_idle = at91sam9_idle;
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arm_pm_restart = at91sam9_alt_restart;
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at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9260_gpio, 3);
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}
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
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7, /* Advanced Interrupt Controller */
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7, /* System Peripherals */
|
|
1, /* Parallel IO Controller A */
|
|
1, /* Parallel IO Controller B */
|
|
1, /* Parallel IO Controller C */
|
|
0, /* Analog-to-Digital Converter */
|
|
5, /* USART 0 */
|
|
5, /* USART 1 */
|
|
5, /* USART 2 */
|
|
0, /* Multimedia Card Interface */
|
|
2, /* USB Device Port */
|
|
6, /* Two-Wire Interface */
|
|
5, /* Serial Peripheral Interface 0 */
|
|
5, /* Serial Peripheral Interface 1 */
|
|
5, /* Serial Synchronous Controller */
|
|
0,
|
|
0,
|
|
0, /* Timer Counter 0 */
|
|
0, /* Timer Counter 1 */
|
|
0, /* Timer Counter 2 */
|
|
2, /* USB Host port */
|
|
3, /* Ethernet */
|
|
0, /* Image Sensor Interface */
|
|
5, /* USART 3 */
|
|
5, /* USART 4 */
|
|
5, /* USART 5 */
|
|
0, /* Timer Counter 3 */
|
|
0, /* Timer Counter 4 */
|
|
0, /* Timer Counter 5 */
|
|
0, /* Advanced Interrupt Controller */
|
|
0, /* Advanced Interrupt Controller */
|
|
0, /* Advanced Interrupt Controller */
|
|
};
|
|
|
|
AT91_SOC_START(at91sam9260)
|
|
.map_io = at91sam9260_map_io,
|
|
.default_irq_priority = at91sam9260_default_irq_priority,
|
|
.extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
|
|
| (1 << AT91SAM9260_ID_IRQ2),
|
|
.ioremap_registers = at91sam9260_ioremap_registers,
|
|
.register_clocks = at91sam9260_register_clocks,
|
|
.init = at91sam9260_initialize,
|
|
AT91_SOC_END
|