b359e8a434
Uses xsave/xrstor (instead of traditional fxsave/fxrstor) in context switch when available. Introduces TS_XSAVE flag, which determine the need to use xsave/xrstor instructions during context switch instead of the legacy fxsave/fxrstor instructions. Thread-synchronous status word is already in L1 cache during this code patch and thus minimizes the performance penality compared to (cpu_has_xsave) checks. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
59 lines
1.4 KiB
C
59 lines
1.4 KiB
C
#ifndef __ASM_X86_XSAVE_H
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#define __ASM_X86_XSAVE_H
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#include <asm/processor.h>
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#include <asm/i387.h>
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#define XSTATE_FP 0x1
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#define XSTATE_SSE 0x2
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#define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
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#define FXSAVE_SIZE 512
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/*
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* These are the features that the OS can handle currently.
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*/
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#define XCNTXT_LMASK (XSTATE_FP | XSTATE_SSE)
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#define XCNTXT_HMASK 0x0
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#ifdef CONFIG_X86_64
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#define REX_PREFIX "0x48, "
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#else
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#define REX_PREFIX
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#endif
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extern unsigned int xstate_size, pcntxt_hmask, pcntxt_lmask;
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extern struct xsave_struct *init_xstate_buf;
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extern void xsave_cntxt_init(void);
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extern void xsave_init(void);
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extern int init_fpu(struct task_struct *child);
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static inline int xrstor_checking(struct xsave_struct *fx)
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{
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int err;
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asm volatile("1: .byte " REX_PREFIX "0x0f,0xae,0x2f\n\t"
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"2:\n"
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".section .fixup,\"ax\"\n"
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"3: movl $-1,%[err]\n"
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" jmp 2b\n"
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".previous\n"
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_ASM_EXTABLE(1b, 3b)
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: [err] "=r" (err)
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: "D" (fx), "m" (*fx), "a" (-1), "d" (-1), "0" (0)
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: "memory");
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return err;
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}
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static inline void xsave(struct task_struct *tsk)
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{
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/* This, however, we can work around by forcing the compiler to select
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an addressing mode that doesn't require extended registers. */
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__asm__ __volatile__(".byte " REX_PREFIX "0x0f,0xae,0x27"
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: : "D" (&(tsk->thread.xstate->xsave)),
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"a" (-1), "d"(-1) : "memory");
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}
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#endif
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