b2d4383480
Choose PAGE_OFFSET dynamically based upon cpu type. Original UltraSPARC-I (spitfire) chips only supported a 44-bit virtual address space. Newer chips (T4 and later) support 52-bit virtual addresses and up to 47-bits of physical memory space. Therefore we have to adjust PAGE_SIZE dynamically based upon the capabilities of the chip. Note that this change alone does not allow us to support > 43-bit physical memory, to do that we need to re-arrange our page table support. The current encodings of the pmd_t and pgd_t pointers restricts us to "32 + 11" == 43 bits. This change can waste quite a bit of memory for the various tables. In particular, a future change should work to size and allocate kern_linear_bitmap[] and sparc64_valid_addr_bitmap[] dynamically. This isn't easy as we really cannot take a TLB miss when accessing kern_linear_bitmap[]. We'd have to lock it into the TLB or similar. Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Bob Picco <bob.picco@oracle.com> |
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extable.c | ||
fault_32.c | ||
fault_64.c | ||
gup.c | ||
highmem.c | ||
hugetlbpage.c | ||
hypersparc.S | ||
init_32.c | ||
init_64.c | ||
init_64.h | ||
io-unit.c | ||
iommu.c | ||
leon_mm.c | ||
Makefile | ||
srmmu.c | ||
srmmu.h | ||
srmmu_access.S | ||
swift.S | ||
tlb.c | ||
tsb.c | ||
tsunami.S | ||
ultra.S | ||
viking.S |