b14e840d04
The document says: |2.1 Problem description | When at least two USB devices are simultaneously running, it is observed that | sometimes the INT corresponding to one of the USB devices stops occurring. This may | be observed sometimes with USB-to-serial or USB-to-network devices. | The problem is not noticed when only USB mass storage devices are running. |2.2 Implication | This issue is because of the clearing of the respective Done Map bit on reading the ATL | PTD Done Map register when an INT is generated by another PTD completion, but is not | found set on that read access. In this situation, the respective Done Map bit will remain | reset and no further INT will be asserted so the data transfer corresponding to that USB | device will stop. |2.3 Workaround | An SOF INT can be used instead of an ATL INT with polling on Done bits. A time-out can | be implemented and if a certain Done bit is never set, verification of the PTD completion | can be done by reading PTD contents (valid bit). | This is a proven workaround implemented in software. Russell King run into this with an USB-to-serial converter. This patch implements his suggestion to enable the high frequent SOF interrupt only at the time we have ATL packages queued. It goes even one step further and enables the SOF interrupt only if we have more than one ATL packet queued at the same time. Cc: <stable@kernel.org> # [2.6.35.x, 2.6.36.x, 2.6.37.x] Tested-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
230 lines
6.2 KiB
C
230 lines
6.2 KiB
C
#ifndef _ISP1760_HCD_H_
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#define _ISP1760_HCD_H_
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/* exports for if */
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struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
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int irq, unsigned long irqflags,
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struct device *dev, const char *busname,
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unsigned int devflags);
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int init_kmem_once(void);
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void deinit_kmem_cache(void);
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/* EHCI capability registers */
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#define HC_CAPLENGTH 0x00
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#define HC_HCSPARAMS 0x04
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#define HC_HCCPARAMS 0x08
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/* EHCI operational registers */
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#define HC_USBCMD 0x20
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#define HC_USBSTS 0x24
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#define HC_FRINDEX 0x2c
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#define HC_CONFIGFLAG 0x60
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#define HC_PORTSC1 0x64
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#define HC_ISO_PTD_DONEMAP_REG 0x130
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#define HC_ISO_PTD_SKIPMAP_REG 0x134
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#define HC_ISO_PTD_LASTPTD_REG 0x138
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#define HC_INT_PTD_DONEMAP_REG 0x140
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#define HC_INT_PTD_SKIPMAP_REG 0x144
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#define HC_INT_PTD_LASTPTD_REG 0x148
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#define HC_ATL_PTD_DONEMAP_REG 0x150
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#define HC_ATL_PTD_SKIPMAP_REG 0x154
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#define HC_ATL_PTD_LASTPTD_REG 0x158
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/* Configuration Register */
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#define HC_HW_MODE_CTRL 0x300
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#define ALL_ATX_RESET (1 << 31)
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#define HW_ANA_DIGI_OC (1 << 15)
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#define HW_DATA_BUS_32BIT (1 << 8)
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#define HW_DACK_POL_HIGH (1 << 6)
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#define HW_DREQ_POL_HIGH (1 << 5)
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#define HW_INTR_HIGH_ACT (1 << 2)
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#define HW_INTR_EDGE_TRIG (1 << 1)
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#define HW_GLOBAL_INTR_EN (1 << 0)
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#define HC_CHIP_ID_REG 0x304
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#define HC_SCRATCH_REG 0x308
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#define HC_RESET_REG 0x30c
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#define SW_RESET_RESET_HC (1 << 1)
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#define SW_RESET_RESET_ALL (1 << 0)
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#define HC_BUFFER_STATUS_REG 0x334
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#define ATL_BUFFER 0x1
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#define INT_BUFFER 0x2
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#define ISO_BUFFER 0x4
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#define BUFFER_MAP 0x7
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#define HC_MEMORY_REG 0x33c
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#define ISP_BANK(x) ((x) << 16)
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#define HC_PORT1_CTRL 0x374
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#define PORT1_POWER (3 << 3)
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#define PORT1_INIT1 (1 << 7)
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#define PORT1_INIT2 (1 << 23)
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#define HW_OTG_CTRL_SET 0x374
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#define HW_OTG_CTRL_CLR 0x376
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/* Interrupt Register */
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#define HC_INTERRUPT_REG 0x310
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#define HC_INTERRUPT_ENABLE 0x314
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#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT | HC_EOT_INT)
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#define INTERRUPT_ENABLE_SOT_MASK (HC_INTL_INT | HC_SOT_INT | HC_EOT_INT)
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#define HC_ISO_INT (1 << 9)
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#define HC_ATL_INT (1 << 8)
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#define HC_INTL_INT (1 << 7)
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#define HC_EOT_INT (1 << 3)
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#define HC_SOT_INT (1 << 1)
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#define HC_ISO_IRQ_MASK_OR_REG 0x318
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#define HC_INT_IRQ_MASK_OR_REG 0x31C
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#define HC_ATL_IRQ_MASK_OR_REG 0x320
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#define HC_ISO_IRQ_MASK_AND_REG 0x324
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#define HC_INT_IRQ_MASK_AND_REG 0x328
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#define HC_ATL_IRQ_MASK_AND_REG 0x32C
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/* Register sets */
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#define HC_BEGIN_OF_ATL 0x0c00
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#define HC_BEGIN_OF_INT 0x0800
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#define HC_BEGIN_OF_ISO 0x0400
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#define HC_BEGIN_OF_PAYLOAD 0x1000
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/* urb state*/
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#define DELETE_URB (0x0008)
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#define NO_TRANSFER_ACTIVE (0xffffffff)
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#define ATL_REGS_OFFSET (0xc00)
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#define INT_REGS_OFFSET (0x800)
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/* Philips Transfer Descriptor (PTD) */
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struct ptd {
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__le32 dw0;
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__le32 dw1;
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__le32 dw2;
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__le32 dw3;
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__le32 dw4;
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__le32 dw5;
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__le32 dw6;
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__le32 dw7;
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};
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struct inter_packet_info {
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void *data_buffer;
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u32 payload;
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#define PTD_FIRE_NEXT (1 << 0)
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#define PTD_URB_FINISHED (1 << 1)
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struct urb *urb;
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struct isp1760_qh *qh;
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struct isp1760_qtd *qtd;
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};
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typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
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struct isp1760_qtd *qtd);
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#define isp1760_dbg(priv, fmt, args...) \
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dev_dbg(priv_to_hcd(priv)->self.controller, fmt, ##args)
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#define isp1760_info(priv, fmt, args...) \
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dev_info(priv_to_hcd(priv)->self.controller, fmt, ##args)
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#define isp1760_err(priv, fmt, args...) \
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dev_err(priv_to_hcd(priv)->self.controller, fmt, ##args)
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/*
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* Device flags that can vary from board to board. All of these
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* indicate the most "atypical" case, so that a devflags of 0 is
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* a sane default configuration.
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*/
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#define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */
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#define ISP1760_FLAG_OTG_EN 0x00000004 /* Port 1 supports OTG */
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#define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */
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#define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */
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#define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */
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#define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */
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#define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */
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#define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */
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/* chip memory management */
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struct memory_chunk {
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unsigned int start;
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unsigned int size;
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unsigned int free;
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};
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/*
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* 60kb divided in:
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* - 32 blocks @ 256 bytes
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* - 20 blocks @ 1024 bytes
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* - 4 blocks @ 8192 bytes
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*/
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#define BLOCK_1_NUM 32
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#define BLOCK_2_NUM 20
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#define BLOCK_3_NUM 4
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#define BLOCK_1_SIZE 256
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#define BLOCK_2_SIZE 1024
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#define BLOCK_3_SIZE 8192
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#define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM)
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#define PAYLOAD_SIZE 0xf000
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/* I saw if some reloads if the pointer was negative */
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#define ISP1760_NULL_POINTER (0x400)
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/* ATL */
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/* DW0 */
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#define PTD_VALID 1
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#define PTD_LENGTH(x) (((u32) x) << 3)
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#define PTD_MAXPACKET(x) (((u32) x) << 18)
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#define PTD_MULTI(x) (((u32) x) << 29)
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#define PTD_ENDPOINT(x) (((u32) x) << 31)
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/* DW1 */
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#define PTD_DEVICE_ADDR(x) (((u32) x) << 3)
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#define PTD_PID_TOKEN(x) (((u32) x) << 10)
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#define PTD_TRANS_BULK ((u32) 2 << 12)
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#define PTD_TRANS_INT ((u32) 3 << 12)
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#define PTD_TRANS_SPLIT ((u32) 1 << 14)
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#define PTD_SE_USB_LOSPEED ((u32) 2 << 16)
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#define PTD_PORT_NUM(x) (((u32) x) << 18)
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#define PTD_HUB_NUM(x) (((u32) x) << 25)
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#define PTD_PING(x) (((u32) x) << 26)
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/* DW2 */
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#define PTD_RL_CNT(x) (((u32) x) << 25)
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#define PTD_DATA_START_ADDR(x) (((u32) x) << 8)
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#define BASE_ADDR 0x1000
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/* DW3 */
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#define PTD_CERR(x) (((u32) x) << 23)
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#define PTD_NAC_CNT(x) (((u32) x) << 19)
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#define PTD_ACTIVE ((u32) 1 << 31)
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#define PTD_DATA_TOGGLE(x) (((u32) x) << 25)
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#define DW3_HALT_BIT (1 << 30)
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#define DW3_ERROR_BIT (1 << 28)
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#define DW3_QTD_ACTIVE (1 << 31)
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#define INT_UNDERRUN (1 << 2)
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#define INT_BABBLE (1 << 1)
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#define INT_EXACT (1 << 0)
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#define DW1_GET_PID(x) (((x) >> 10) & 0x3)
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#define PTD_XFERRED_LENGTH(x) ((x) & 0x7fff)
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#define PTD_XFERRED_LENGTH_LO(x) ((x) & 0x7ff)
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#define SETUP_PID (2)
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#define IN_PID (1)
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#define OUT_PID (0)
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#define GET_QTD_TOKEN_TYPE(x) ((x) & 0x3)
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#define DATA_TOGGLE (1 << 31)
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#define GET_DATA_TOGGLE(x) ((x) >> 31)
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/* Errata 1 */
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#define RL_COUNTER (0)
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#define NAK_COUNTER (0)
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#define ERR_COUNTER (2)
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#define HC_ATL_PL_SIZE (8192)
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#endif
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