990dbcc685
A definition like:
called with PVR_IS_FULL(foo) will be preprocessed to:
(foo.foo[0] & PVR0_PVR_FULL_MASK)
^^^
So to fix this and ensure the preprocessor compiles calls correctly:
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
226 lines
8.6 KiB
C
226 lines
8.6 KiB
C
/*
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* Support for the MicroBlaze PVR (Processor Version Register)
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*
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* Copyright (C) 2009 - 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007 John Williams <john.williams@petalogix.com>
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* Copyright (C) 2007 - 2011 PetaLogix
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*/
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#ifndef _ASM_MICROBLAZE_PVR_H
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#define _ASM_MICROBLAZE_PVR_H
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#define PVR_MSR_BIT 0x400
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struct pvr_s {
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unsigned pvr[12];
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};
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/* The following taken from Xilinx's standalone BSP pvr.h */
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/* Basic PVR mask */
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#define PVR0_PVR_FULL_MASK 0x80000000
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#define PVR0_USE_BARREL_MASK 0x40000000
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#define PVR0_USE_DIV_MASK 0x20000000
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#define PVR0_USE_HW_MUL_MASK 0x10000000
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#define PVR0_USE_FPU_MASK 0x08000000
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#define PVR0_USE_EXC_MASK 0x04000000
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#define PVR0_USE_ICACHE_MASK 0x02000000
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#define PVR0_USE_DCACHE_MASK 0x01000000
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#define PVR0_USE_MMU 0x00800000
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#define PVR0_USE_BTC 0x00400000
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#define PVR0_ENDI 0x00200000
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#define PVR0_VERSION_MASK 0x0000FF00
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#define PVR0_USER1_MASK 0x000000FF
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/* User 2 PVR mask */
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#define PVR1_USER2_MASK 0xFFFFFFFF
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/* Configuration PVR masks */
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#define PVR2_D_OPB_MASK 0x80000000 /* or AXI */
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#define PVR2_D_LMB_MASK 0x40000000
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#define PVR2_I_OPB_MASK 0x20000000 /* or AXI */
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#define PVR2_I_LMB_MASK 0x10000000
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#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
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#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
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#define PVR2_D_PLB_MASK 0x02000000 /* new */
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#define PVR2_I_PLB_MASK 0x01000000 /* new */
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#define PVR2_INTERCONNECT 0x00800000 /* new */
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#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
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#define PVR2_USE_FSL_EXC 0x00040000 /* new */
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#define PVR2_USE_MSR_INSTR 0x00020000
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#define PVR2_USE_PCMP_INSTR 0x00010000
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#define PVR2_AREA_OPTIMISED 0x00008000
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#define PVR2_USE_BARREL_MASK 0x00004000
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#define PVR2_USE_DIV_MASK 0x00002000
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#define PVR2_USE_HW_MUL_MASK 0x00001000
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#define PVR2_USE_FPU_MASK 0x00000800
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#define PVR2_USE_MUL64_MASK 0x00000400
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#define PVR2_USE_FPU2_MASK 0x00000200 /* new */
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#define PVR2_USE_IPLBEXC 0x00000100
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#define PVR2_USE_DPLBEXC 0x00000080
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#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
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#define PVR2_UNALIGNED_EXC_MASK 0x00000020
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#define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
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#define PVR2_IOPB_BUS_EXC_MASK 0x00000008 /* or AXI */
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#define PVR2_DOPB_BUS_EXC_MASK 0x00000004 /* or AXI */
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#define PVR2_DIV_ZERO_EXC_MASK 0x00000002
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#define PVR2_FPU_EXC_MASK 0x00000001
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/* Debug and exception PVR masks */
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#define PVR3_DEBUG_ENABLED_MASK 0x80000000
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#define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
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#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
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#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
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#define PVR3_FSL_LINKS_MASK 0x00000380
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/* ICache config PVR masks */
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#define PVR4_USE_ICACHE_MASK 0x80000000 /* ICU */
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#define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 /* ICTS */
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#define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 /* ICW */
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#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 /* ICLL */
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#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 /* ICBS */
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#define PVR4_ICACHE_ALWAYS_USED 0x00008000 /* IAU */
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#define PVR4_ICACHE_INTERFACE 0x00002000 /* ICI */
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/* DCache config PVR masks */
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#define PVR5_USE_DCACHE_MASK 0x80000000 /* DCU */
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#define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 /* DCTS */
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#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 /* DCW */
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#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 /* DCLL */
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#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 /* DCBS */
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#define PVR5_DCACHE_ALWAYS_USED 0x00008000 /* DAU */
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#define PVR5_DCACHE_USE_WRITEBACK 0x00004000 /* DWB */
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#define PVR5_DCACHE_INTERFACE 0x00002000 /* DCI */
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/* ICache base address PVR mask */
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#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
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/* ICache high address PVR mask */
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#define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
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/* DCache base address PVR mask */
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#define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
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/* DCache high address PVR mask */
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#define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
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/* Target family PVR mask */
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#define PVR10_TARGET_FAMILY_MASK 0xFF000000
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/* MMU descrtiption */
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#define PVR11_USE_MMU 0xC0000000
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#define PVR11_MMU_ITLB_SIZE 0x38000000
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#define PVR11_MMU_DTLB_SIZE 0x07000000
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#define PVR11_MMU_TLB_ACCESS 0x00C00000
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#define PVR11_MMU_ZONES 0x003C0000
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/* MSR Reset value PVR mask */
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#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
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/* PVR access macros */
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#define PVR_IS_FULL(_pvr) (_pvr.pvr[0] & PVR0_PVR_FULL_MASK)
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#define PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & PVR0_USE_BARREL_MASK)
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#define PVR_USE_DIV(_pvr) (_pvr.pvr[0] & PVR0_USE_DIV_MASK)
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#define PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & PVR0_USE_HW_MUL_MASK)
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#define PVR_USE_FPU(_pvr) (_pvr.pvr[0] & PVR0_USE_FPU_MASK)
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#define PVR_USE_FPU2(_pvr) (_pvr.pvr[2] & PVR2_USE_FPU2_MASK)
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#define PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_ICACHE_MASK)
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#define PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_DCACHE_MASK)
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#define PVR_VERSION(_pvr) ((_pvr.pvr[0] & PVR0_VERSION_MASK) >> 8)
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#define PVR_USER1(_pvr) (_pvr.pvr[0] & PVR0_USER1_MASK)
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#define PVR_USER2(_pvr) (_pvr.pvr[1] & PVR1_USER2_MASK)
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#define PVR_D_OPB(_pvr) (_pvr.pvr[2] & PVR2_D_OPB_MASK)
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#define PVR_D_LMB(_pvr) (_pvr.pvr[2] & PVR2_D_LMB_MASK)
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#define PVR_I_OPB(_pvr) (_pvr.pvr[2] & PVR2_I_OPB_MASK)
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#define PVR_I_LMB(_pvr) (_pvr.pvr[2] & PVR2_I_LMB_MASK)
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#define PVR_INTERRUPT_IS_EDGE(_pvr) \
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(_pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK)
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#define PVR_EDGE_IS_POSITIVE(_pvr) \
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(_pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK)
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#define PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_MSR_INSTR)
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#define PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_PCMP_INSTR)
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#define PVR_AREA_OPTIMISED(_pvr) (_pvr.pvr[2] & PVR2_AREA_OPTIMISED)
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#define PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & PVR2_USE_MUL64_MASK)
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#define PVR_OPCODE_0x0_ILLEGAL(_pvr) \
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(_pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK)
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#define PVR_UNALIGNED_EXCEPTION(_pvr) \
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(_pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK)
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#define PVR_ILL_OPCODE_EXCEPTION(_pvr) \
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(_pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK)
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#define PVR_IOPB_BUS_EXCEPTION(_pvr) \
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(_pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK)
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#define PVR_DOPB_BUS_EXCEPTION(_pvr) \
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(_pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK)
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#define PVR_DIV_ZERO_EXCEPTION(_pvr) \
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(_pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK)
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#define PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_FPU_EXC_MASK)
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#define PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_USE_EXTEND_FSL)
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#define PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK)
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#define PVR_NUMBER_OF_PC_BRK(_pvr) \
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((_pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
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#define PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) \
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((_pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
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#define PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) \
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((_pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
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#define PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7)
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#define PVR_ICACHE_ADDR_TAG_BITS(_pvr) \
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((_pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
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#define PVR_ICACHE_USE_FSL(_pvr) \
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(_pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK)
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#define PVR_ICACHE_ALLOW_WR(_pvr) \
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(_pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK)
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#define PVR_ICACHE_LINE_LEN(_pvr) \
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(1 << ((_pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21))
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#define PVR_ICACHE_BYTE_SIZE(_pvr) \
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(1 << ((_pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
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#define PVR_DCACHE_ADDR_TAG_BITS(_pvr) \
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((_pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
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#define PVR_DCACHE_USE_FSL(_pvr) (_pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
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#define PVR_DCACHE_ALLOW_WR(_pvr) \
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(_pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
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/* FIXME two shifts on one line needs any comment */
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#define PVR_DCACHE_LINE_LEN(_pvr) \
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(1 << ((_pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
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#define PVR_DCACHE_BYTE_SIZE(_pvr) \
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(1 << ((_pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
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#define PVR_DCACHE_USE_WRITEBACK(_pvr) \
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((_pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
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#define PVR_ICACHE_BASEADDR(_pvr) \
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(_pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
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#define PVR_ICACHE_HIGHADDR(_pvr) \
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(_pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
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#define PVR_DCACHE_BASEADDR(_pvr) \
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(_pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK)
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#define PVR_DCACHE_HIGHADDR(_pvr) \
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(_pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK)
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#define PVR_TARGET_FAMILY(_pvr) \
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((_pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24)
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#define PVR_MSR_RESET_VALUE(_pvr) \
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(_pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
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/* mmu */
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#define PVR_USE_MMU(_pvr) ((_pvr.pvr[11] & PVR11_USE_MMU) >> 30)
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#define PVR_MMU_ITLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_ITLB_SIZE)
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#define PVR_MMU_DTLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)
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#define PVR_MMU_TLB_ACCESS(_pvr) (_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)
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#define PVR_MMU_ZONES(_pvr) (_pvr.pvr[11] & PVR11_MMU_ZONES)
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/* endian */
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#define PVR_ENDIAN(_pvr) (_pvr.pvr[0] & PVR0_ENDI)
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int cpu_has_pvr(void);
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void get_pvr(struct pvr_s *pvr);
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#endif /* _ASM_MICROBLAZE_PVR_H */
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