023c75c7c8
The name of the I2C2 and I2C3 interrupt should be IIC2 and IIC3 instead of CAN0 and CAN1. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
136 lines
4.2 KiB
C
136 lines
4.2 KiB
C
/* linux/arch/arm/mach-s5pv210/include/mach/irqs.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5PV210 - IRQ definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H __FILE__
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#include <plat/irqs.h>
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/* VIC0: System, DMA, Timer */
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#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
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#define IRQ_BATF S5P_IRQ_VIC0(17)
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#define IRQ_MDMA S5P_IRQ_VIC0(18)
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#define IRQ_PDMA0 S5P_IRQ_VIC0(19)
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#define IRQ_PDMA1 S5P_IRQ_VIC0(20)
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#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21)
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#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22)
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#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23)
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#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24)
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#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25)
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#define IRQ_SYSTIMER S5P_IRQ_VIC0(26)
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#define IRQ_WDT S5P_IRQ_VIC0(27)
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#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28)
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#define IRQ_RTC_TIC S5P_IRQ_VIC0(29)
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#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
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#define IRQ_FIMC3 S5P_IRQ_VIC0(31)
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/* VIC1: ARM, Power, Memory, Connectivity, Storage */
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#define IRQ_PMU S5P_IRQ_VIC1(0)
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#define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
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#define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
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#define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
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#define IRQ_CORTEX4 S5P_IRQ_VIC1(4)
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#define IRQ_IEMAPC S5P_IRQ_VIC1(5)
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#define IRQ_IEMIEC S5P_IRQ_VIC1(6)
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#define IRQ_ONENAND S5P_IRQ_VIC1(7)
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#define IRQ_NFC S5P_IRQ_VIC1(8)
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#define IRQ_CFCON S5P_IRQ_VIC1(9)
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#define IRQ_UART0 S5P_IRQ_VIC1(10)
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#define IRQ_UART1 S5P_IRQ_VIC1(11)
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#define IRQ_UART2 S5P_IRQ_VIC1(12)
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#define IRQ_UART3 S5P_IRQ_VIC1(13)
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#define IRQ_IIC S5P_IRQ_VIC1(14)
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#define IRQ_SPI0 S5P_IRQ_VIC1(15)
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#define IRQ_SPI1 S5P_IRQ_VIC1(16)
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#define IRQ_SPI2 S5P_IRQ_VIC1(17)
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#define IRQ_IRDA S5P_IRQ_VIC1(18)
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#define IRQ_IIC2 S5P_IRQ_VIC1(19)
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#define IRQ_IIC3 S5P_IRQ_VIC1(20)
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#define IRQ_HSIRX S5P_IRQ_VIC1(21)
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#define IRQ_HSITX S5P_IRQ_VIC1(22)
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#define IRQ_UHOST S5P_IRQ_VIC1(23)
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#define IRQ_OTG S5P_IRQ_VIC1(24)
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#define IRQ_MSM S5P_IRQ_VIC1(25)
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#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
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#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
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#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
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#define IRQ_MIPICSI S5P_IRQ_VIC1(29)
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#define IRQ_MIPIDSI S5P_IRQ_VIC1(30)
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#define IRQ_ONENAND_AUDI S5P_IRQ_VIC1(31)
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/* VIC2: Multimedia, Audio, Security */
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#define IRQ_LCD0 S5P_IRQ_VIC2(0)
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#define IRQ_LCD1 S5P_IRQ_VIC2(1)
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#define IRQ_LCD2 S5P_IRQ_VIC2(2)
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#define IRQ_LCD3 S5P_IRQ_VIC2(3)
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#define IRQ_ROTATOR S5P_IRQ_VIC2(4)
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#define IRQ_FIMC0 S5P_IRQ_VIC2(5)
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#define IRQ_FIMC1 S5P_IRQ_VIC2(6)
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#define IRQ_FIMC2 S5P_IRQ_VIC2(7)
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#define IRQ_JPEG S5P_IRQ_VIC2(8)
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#define IRQ_2D S5P_IRQ_VIC2(9)
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#define IRQ_3D S5P_IRQ_VIC2(10)
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#define IRQ_MIXER S5P_IRQ_VIC2(11)
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#define IRQ_HDMI S5P_IRQ_VIC2(12)
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#define IRQ_IIC1 S5P_IRQ_VIC2(13)
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#define IRQ_MFC S5P_IRQ_VIC2(14)
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#define IRQ_TVENC S5P_IRQ_VIC2(15)
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#define IRQ_I2S0 S5P_IRQ_VIC2(16)
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#define IRQ_I2S1 S5P_IRQ_VIC2(17)
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#define IRQ_I2S2 S5P_IRQ_VIC2(18)
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#define IRQ_AC97 S5P_IRQ_VIC2(19)
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#define IRQ_PCM0 S5P_IRQ_VIC2(20)
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#define IRQ_PCM1 S5P_IRQ_VIC2(21)
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#define IRQ_SPDIF S5P_IRQ_VIC2(22)
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#define IRQ_ADC S5P_IRQ_VIC2(23)
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#define IRQ_PENDN S5P_IRQ_VIC2(24)
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#define IRQ_TC IRQ_PENDN
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#define IRQ_KEYPAD S5P_IRQ_VIC2(25)
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#define IRQ_CG S5P_IRQ_VIC2(26)
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#define IRQ_SEC S5P_IRQ_VIC2(27)
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#define IRQ_SECRX S5P_IRQ_VIC2(28)
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#define IRQ_SECTX S5P_IRQ_VIC2(29)
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#define IRQ_SDMIRQ S5P_IRQ_VIC2(30)
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#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
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/* VIC3: Etc */
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#define IRQ_IPC S5P_IRQ_VIC3(0)
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#define IRQ_HOSTIF S5P_IRQ_VIC3(1)
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#define IRQ_HSMMC3 S5P_IRQ_VIC3(2)
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#define IRQ_CEC S5P_IRQ_VIC3(3)
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#define IRQ_TSI S5P_IRQ_VIC3(4)
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#define IRQ_MDNIE0 S5P_IRQ_VIC3(5)
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#define IRQ_MDNIE1 S5P_IRQ_VIC3(6)
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#define IRQ_MDNIE2 S5P_IRQ_VIC3(7)
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#define IRQ_MDNIE3 S5P_IRQ_VIC3(8)
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#define IRQ_VIC_END S5P_IRQ_VIC3(31)
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#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
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#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
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/* GPIO interrupt */
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#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1)
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#define S5P_GPIOINT_GROUP_MAXNR 22
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/* Set the default NR_IRQS */
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#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
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/* Compatibility */
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#define IRQ_LCD_FIFO IRQ_LCD0
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#define IRQ_LCD_VSYNC IRQ_LCD1
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#define IRQ_LCD_SYSTEM IRQ_LCD2
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#endif /* ASM_ARCH_IRQS_H */
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