99dd871330
The UV TLB shootdown mechanism needs a system interrupt vector. Its vector had been hardcoded as 200, but needs to moved to the reserved system vector range so that it does not collide with some device vector. This is still temporary until dynamic system IRQ allocation is provided. But it will be needed when real UV hardware becomes available and runs 2.6.27. Signed-off-by: Cliff Wickman <cpw@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
182 lines
5 KiB
C
182 lines
5 KiB
C
#ifndef _ASM_IRQ_VECTORS_H
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#define _ASM_IRQ_VECTORS_H
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#include <linux/threads.h>
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#define NMI_VECTOR 0x02
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/*
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* IDT vectors usable for external interrupt sources start
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* at 0x20:
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*/
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#define FIRST_EXTERNAL_VECTOR 0x20
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#ifdef CONFIG_X86_32
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# define SYSCALL_VECTOR 0x80
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#else
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# define IA32_SYSCALL_VECTOR 0x80
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#endif
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/*
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* Reserve the lowest usable priority level 0x20 - 0x2f for triggering
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* cleanup after irq migration on 64 bit.
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*/
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#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
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/*
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* Vectors 0x20-0x2f are used for ISA interrupts on 32 bit.
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* Vectors 0x30-0x3f are used for ISA interrupts on 64 bit.
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*/
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#ifdef CONFIG_X86_32
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#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR)
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#else
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#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10)
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#endif
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#define IRQ1_VECTOR (IRQ0_VECTOR + 1)
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#define IRQ2_VECTOR (IRQ0_VECTOR + 2)
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#define IRQ3_VECTOR (IRQ0_VECTOR + 3)
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#define IRQ4_VECTOR (IRQ0_VECTOR + 4)
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#define IRQ5_VECTOR (IRQ0_VECTOR + 5)
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#define IRQ6_VECTOR (IRQ0_VECTOR + 6)
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#define IRQ7_VECTOR (IRQ0_VECTOR + 7)
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#define IRQ8_VECTOR (IRQ0_VECTOR + 8)
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#define IRQ9_VECTOR (IRQ0_VECTOR + 9)
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#define IRQ10_VECTOR (IRQ0_VECTOR + 10)
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#define IRQ11_VECTOR (IRQ0_VECTOR + 11)
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#define IRQ12_VECTOR (IRQ0_VECTOR + 12)
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#define IRQ13_VECTOR (IRQ0_VECTOR + 13)
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#define IRQ14_VECTOR (IRQ0_VECTOR + 14)
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#define IRQ15_VECTOR (IRQ0_VECTOR + 15)
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/*
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* Special IRQ vectors used by the SMP architecture, 0xf0-0xff
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*
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* some of the following vectors are 'rare', they are merged
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* into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
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* TLB, reschedule and local APIC vectors are performance-critical.
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*
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* Vectors 0xf0-0xfa are free (reserved for future Linux use).
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*/
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#ifdef CONFIG_X86_32
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# define SPURIOUS_APIC_VECTOR 0xff
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# define ERROR_APIC_VECTOR 0xfe
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# define INVALIDATE_TLB_VECTOR 0xfd
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# define RESCHEDULE_VECTOR 0xfc
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# define CALL_FUNCTION_VECTOR 0xfb
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# define CALL_FUNCTION_SINGLE_VECTOR 0xfa
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# define THERMAL_APIC_VECTOR 0xf0
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#else
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#define SPURIOUS_APIC_VECTOR 0xff
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#define ERROR_APIC_VECTOR 0xfe
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#define RESCHEDULE_VECTOR 0xfd
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#define CALL_FUNCTION_VECTOR 0xfc
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#define CALL_FUNCTION_SINGLE_VECTOR 0xfb
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#define THERMAL_APIC_VECTOR 0xfa
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#define THRESHOLD_APIC_VECTOR 0xf9
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#define UV_BAU_MESSAGE 0xf8
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#define INVALIDATE_TLB_VECTOR_END 0xf7
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#define INVALIDATE_TLB_VECTOR_START 0xf0 /* f0-f7 used for TLB flush */
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#define NUM_INVALIDATE_TLB_VECTORS 8
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#endif
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/*
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* Local APIC timer IRQ vector is on a different priority level,
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* to work around the 'lost local interrupt if more than 2 IRQ
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* sources per level' errata.
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*/
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#define LOCAL_TIMER_VECTOR 0xef
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/*
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* First APIC vector available to drivers: (vectors 0x30-0xee) we
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* start at 0x31(0x41) to spread out vectors evenly between priority
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* levels. (0x80 is the syscall vector)
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*/
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#ifdef CONFIG_X86_32
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# define FIRST_DEVICE_VECTOR 0x31
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#else
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# define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
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#endif
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#define NR_VECTORS 256
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#define FPU_IRQ 13
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#define FIRST_VM86_IRQ 3
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#define LAST_VM86_IRQ 15
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#define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15)
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#ifdef CONFIG_X86_64
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# if NR_CPUS < MAX_IO_APICS
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# define NR_IRQS (NR_VECTORS + (32 * NR_CPUS))
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# else
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# define NR_IRQS (NR_VECTORS + (32 * MAX_IO_APICS))
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# endif
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# define NR_IRQ_VECTORS NR_IRQS
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#elif !defined(CONFIG_X86_VOYAGER)
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# if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_PARAVIRT) || defined(CONFIG_X86_VISWS)
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# define NR_IRQS 224
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# if (224 >= 32 * NR_CPUS)
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# define NR_IRQ_VECTORS NR_IRQS
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# else
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# define NR_IRQ_VECTORS (32 * NR_CPUS)
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# endif
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# else /* IO_APIC || PARAVIRT */
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# define NR_IRQS 16
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# define NR_IRQ_VECTORS NR_IRQS
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# endif
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#else /* !VISWS && !VOYAGER */
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# define NR_IRQS 224
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# define NR_IRQ_VECTORS NR_IRQS
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#endif /* VISWS */
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/* Voyager specific defines */
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/* These define the CPIs we use in linux */
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#define VIC_CPI_LEVEL0 0
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#define VIC_CPI_LEVEL1 1
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/* now the fake CPIs */
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#define VIC_TIMER_CPI 2
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#define VIC_INVALIDATE_CPI 3
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#define VIC_RESCHEDULE_CPI 4
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#define VIC_ENABLE_IRQ_CPI 5
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#define VIC_CALL_FUNCTION_CPI 6
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#define VIC_CALL_FUNCTION_SINGLE_CPI 7
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/* Now the QIC CPIs: Since we don't need the two initial levels,
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* these are 2 less than the VIC CPIs */
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#define QIC_CPI_OFFSET 1
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#define QIC_TIMER_CPI (VIC_TIMER_CPI - QIC_CPI_OFFSET)
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#define QIC_INVALIDATE_CPI (VIC_INVALIDATE_CPI - QIC_CPI_OFFSET)
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#define QIC_RESCHEDULE_CPI (VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET)
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#define QIC_ENABLE_IRQ_CPI (VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET)
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#define QIC_CALL_FUNCTION_CPI (VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET)
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#define QIC_CALL_FUNCTION_SINGLE_CPI (VIC_CALL_FUNCTION_SINGLE_CPI - QIC_CPI_OFFSET)
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#define VIC_START_FAKE_CPI VIC_TIMER_CPI
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#define VIC_END_FAKE_CPI VIC_CALL_FUNCTION_SINGLE_CPI
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/* this is the SYS_INT CPI. */
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#define VIC_SYS_INT 8
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#define VIC_CMN_INT 15
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/* This is the boot CPI for alternate processors. It gets overwritten
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* by the above once the system has activated all available processors */
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#define VIC_CPU_BOOT_CPI VIC_CPI_LEVEL0
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#define VIC_CPU_BOOT_ERRATA_CPI (VIC_CPI_LEVEL0 + 8)
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#endif /* _ASM_IRQ_VECTORS_H */
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