64fc2a947a
All low-level PM/SMP code using virt_to_phys() should actually use __pa_symbol() against kernel symbols. Update code where relevant to move away from virt_to_phys(). Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Laura Abbott <labbott@redhat.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
163 lines
3.5 KiB
C
163 lines
3.5 KiB
C
/*
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* arch/arm/mach-sti/platsmp.c
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*
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* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
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* http://www.st.com
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*
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* Cloned from linux/arch/arm/mach-vexpress/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/memblock.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include "smp.h"
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static void write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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sync_cache_w(&pen_release);
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}
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static DEFINE_SPINLOCK(boot_lock);
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static void sti_secondary_init(unsigned int cpu)
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{
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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/*
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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write_pen_release(cpu_logical_map(cpu));
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* it to jump to the secondary entrypoint.
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*/
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *np;
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void __iomem *scu_base;
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u32 __iomem *cpu_strt_ptr;
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u32 release_phys;
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int cpu;
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unsigned long entry_pa = __pa_symbol(sti_secondary_startup);
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np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (np) {
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scu_base = of_iomap(np, 0);
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scu_enable(scu_base);
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of_node_put(np);
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}
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if (max_cpus <= 1)
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return;
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for_each_possible_cpu(cpu) {
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np = of_get_cpu_node(cpu, NULL);
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if (!np)
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continue;
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if (of_property_read_u32(np, "cpu-release-addr",
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&release_phys)) {
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pr_err("CPU %d: missing or invalid cpu-release-addr "
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"property\n", cpu);
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continue;
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}
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/*
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* holding pen is usually configured in SBC DMEM but can also be
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* in RAM.
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*/
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if (!memblock_is_memory(release_phys))
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cpu_strt_ptr =
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ioremap(release_phys, sizeof(release_phys));
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else
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cpu_strt_ptr =
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(u32 __iomem *)phys_to_virt(release_phys);
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__raw_writel(entry_pa, cpu_strt_ptr);
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/*
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* wmb so that data is actually written
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* before cache flush is done
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*/
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smp_wmb();
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sync_cache_w(cpu_strt_ptr);
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if (!memblock_is_memory(release_phys))
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iounmap(cpu_strt_ptr);
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}
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}
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const struct smp_operations sti_smp_ops __initconst = {
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.smp_prepare_cpus = sti_smp_prepare_cpus,
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.smp_secondary_init = sti_secondary_init,
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.smp_boot_secondary = sti_boot_secondary,
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};
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