aed5d5f4c5
This updated patch should fix the compiling errors and remove the extern iommu_pass_through from drivers/pci/intel-iommu.c file. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
125 lines
2.8 KiB
C
125 lines
2.8 KiB
C
/*
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* Dynamic DMA mapping support.
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*/
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/string.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/dmar.h>
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#include <asm/iommu.h>
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#include <asm/machvec.h>
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#include <linux/dma-mapping.h>
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#include <asm/system.h>
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#ifdef CONFIG_DMAR
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#include <linux/kernel.h>
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#include <asm/page.h>
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dma_addr_t bad_dma_address __read_mostly;
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EXPORT_SYMBOL(bad_dma_address);
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static int iommu_sac_force __read_mostly;
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int no_iommu __read_mostly;
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#ifdef CONFIG_IOMMU_DEBUG
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int force_iommu __read_mostly = 1;
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#else
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int force_iommu __read_mostly;
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#endif
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int iommu_pass_through;
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/* Dummy device used for NULL arguments (normally ISA). Better would
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be probably a smaller DMA mask, but this is bug-to-bug compatible
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to i386. */
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struct device fallback_dev = {
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.init_name = "fallback device",
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.dma_mask = &fallback_dev.coherent_dma_mask,
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};
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extern struct dma_map_ops intel_dma_ops;
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static int __init pci_iommu_init(void)
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{
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if (iommu_detected)
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intel_iommu_init();
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return 0;
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}
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/* Must execute after PCI subsystem */
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fs_initcall(pci_iommu_init);
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void pci_iommu_shutdown(void)
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{
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return;
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}
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void __init
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iommu_dma_init(void)
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{
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return;
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}
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int iommu_dma_supported(struct device *dev, u64 mask)
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{
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struct dma_map_ops *ops = platform_dma_get_ops(dev);
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if (ops->dma_supported)
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return ops->dma_supported(dev, mask);
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/* Copied from i386. Doesn't make much sense, because it will
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only work for pci_alloc_coherent.
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The caller just has to use GFP_DMA in this case. */
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if (mask < DMA_BIT_MASK(24))
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return 0;
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/* Tell the device to use SAC when IOMMU force is on. This
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allows the driver to use cheaper accesses in some cases.
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Problem with this is that if we overflow the IOMMU area and
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return DAC as fallback address the device may not handle it
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correctly.
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As a special case some controllers have a 39bit address
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mode that is as efficient as 32bit (aic79xx). Don't force
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SAC for these. Assume all masks <= 40 bits are of this
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type. Normally this doesn't make any difference, but gives
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more gentle handling of IOMMU overflow. */
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if (iommu_sac_force && (mask >= DMA_BIT_MASK(40))) {
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dev_info(dev, "Force SAC with mask %lx\n", mask);
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return 0;
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}
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return 1;
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}
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EXPORT_SYMBOL(iommu_dma_supported);
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void __init pci_iommu_alloc(void)
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{
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dma_ops = &intel_dma_ops;
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dma_ops->sync_single_for_cpu = machvec_dma_sync_single;
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dma_ops->sync_sg_for_cpu = machvec_dma_sync_sg;
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dma_ops->sync_single_for_device = machvec_dma_sync_single;
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dma_ops->sync_sg_for_device = machvec_dma_sync_sg;
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dma_ops->dma_supported = iommu_dma_supported;
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/*
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* The order of these functions is important for
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* fall-back/fail-over reasons
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*/
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detect_intel_iommu();
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#ifdef CONFIG_SWIOTLB
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pci_swiotlb_init();
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#endif
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}
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#endif
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