62b0194368
The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. Contains various improvements from Atish Patra <atish.patra@wdc.com>. Signed-off-by: Dmitriy Cherkasov <dmitriy@oss-tech.org> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> [hch: remove dead code, add SPDX tags, used riscv_of_processor_hart(), minor cleanups, merged hotplug cpu support and other improvements from Atish] Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
113 lines
2.8 KiB
C
113 lines
2.8 KiB
C
/*
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* SMP initialisation and IPI support
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* Based on arch/arm64/kernel/smp.c
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*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2015 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/kernel_stat.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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#include <linux/percpu.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/sched/task_stack.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/sections.h>
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#include <asm/sbi.h>
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void *__cpu_up_stack_pointer[NR_CPUS];
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void *__cpu_up_task_pointer[NR_CPUS];
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void __init smp_prepare_boot_cpu(void)
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{
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}
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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}
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void __init setup_smp(void)
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{
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struct device_node *dn = NULL;
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int hart, im_okay_therefore_i_am = 0;
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while ((dn = of_find_node_by_type(dn, "cpu"))) {
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hart = riscv_of_processor_hart(dn);
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if (hart >= 0) {
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set_cpu_possible(hart, true);
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set_cpu_present(hart, true);
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if (hart == smp_processor_id()) {
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BUG_ON(im_okay_therefore_i_am);
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im_okay_therefore_i_am = 1;
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}
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}
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}
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BUG_ON(!im_okay_therefore_i_am);
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}
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int __cpu_up(unsigned int cpu, struct task_struct *tidle)
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{
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tidle->thread_info.cpu = cpu;
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/*
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* On RISC-V systems, all harts boot on their own accord. Our _start
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* selects the first hart to boot the kernel and causes the remainder
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* of the harts to spin in a loop waiting for their stack pointer to be
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* setup by that main hart. Writing __cpu_up_stack_pointer signals to
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* the spinning harts that they can continue the boot process.
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*/
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smp_mb();
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__cpu_up_stack_pointer[cpu] = task_stack_page(tidle) + THREAD_SIZE;
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__cpu_up_task_pointer[cpu] = tidle;
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while (!cpu_online(cpu))
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cpu_relax();
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return 0;
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}
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void __init smp_cpus_done(unsigned int max_cpus)
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{
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}
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/*
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* C entry point for a secondary processor.
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*/
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asmlinkage void __init smp_callin(void)
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{
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struct mm_struct *mm = &init_mm;
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/* All kernel threads share the same mm context. */
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atomic_inc(&mm->mm_count);
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current->active_mm = mm;
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trap_init();
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notify_cpu_starting(smp_processor_id());
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set_cpu_online(smp_processor_id(), 1);
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local_flush_tlb_all();
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local_irq_enable();
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preempt_disable();
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cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
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}
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