002547b4f8
Majorily based on Hyok Choi's patches, this fixes up the asm-arm header files for mmuless systems. Over and above Hyok's patches: - nommu.h merged into mmu.h (it's only a structure) - nommu_context.h is essentially the same as mmu_context.h, but without the MM switching code. so there's no point having separate files. Also, in memory.h, there's no point #ifndef'ing PHYS_OFFSET and END_MEM - both CONFIG_DRAM_BASE and CONFIG_DRAM_SIZE will always be set by the configuration scripts. Other files have minor formatting changes, but are essentially the same. Hyok's original patches were signed off thusly: Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
123 lines
2.9 KiB
C
123 lines
2.9 KiB
C
/*
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* linux/include/asm-arm/pgtable-nommu.h
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*
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* Copyright (C) 1995-2002 Russell King
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* Copyright (C) 2004 Hyok S. Choi
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASMARM_PGTABLE_NOMMU_H
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#define _ASMARM_PGTABLE_NOMMU_H
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#ifndef __ASSEMBLY__
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#include <linux/config.h>
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#include <linux/slab.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/io.h>
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/*
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* Trivial page table functions.
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*/
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#define pgd_present(pgd) (1)
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#define pgd_none(pgd) (0)
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#define pgd_bad(pgd) (0)
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#define pgd_clear(pgdp)
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#define kern_addr_valid(addr) (1)
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#define pmd_offset(a, b) ((void *)0)
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/* FIXME */
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/*
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* PMD_SHIFT determines the size of the area a second-level page table can map
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* PGDIR_SHIFT determines what a third-level page table entry can map
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*/
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#define PGDIR_SHIFT 21
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/* FIXME */
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#define PAGE_NONE __pgprot(0)
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#define PAGE_SHARED __pgprot(0)
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#define PAGE_COPY __pgprot(0)
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#define PAGE_READONLY __pgprot(0)
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#define PAGE_KERNEL __pgprot(0)
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//extern void paging_init(struct meminfo *, struct machine_desc *);
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#define swapper_pg_dir ((pgd_t *) 0)
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#define __swp_type(x) (0)
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#define __swp_offset(x) (0)
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#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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typedef pte_t *pte_addr_t;
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static inline int pte_file(pte_t pte) { return 0; }
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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#define ZERO_PAGE(vaddr) (virt_to_page(0))
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/*
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* Mark the prot value as uncacheable and unbufferable.
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*/
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#define pgprot_noncached(prot) __pgprot(0)
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#define pgprot_writecombine(prot) __pgprot(0)
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/*
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* These would be in other places but having them here reduces the diffs.
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*/
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extern unsigned int kobjsize(const void *objp);
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extern int is_in_rom(unsigned long);
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/*
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* No page table caches to initialise.
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*/
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#define pgtable_cache_init() do { } while (0)
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#define io_remap_page_range remap_page_range
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#define io_remap_pfn_range remap_pfn_range
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#define MK_IOSPACE_PFN(space, pfn) (pfn)
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#define GET_IOSPACE(pfn) 0
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#define GET_PFN(pfn) (pfn)
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/*
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* All 32bit addresses are effectively valid for vmalloc...
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* Sort of meaningless for non-VM targets.
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*/
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#define VMALLOC_START 0
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#define VMALLOC_END 0xffffffff
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#define FIRST_USER_ADDRESS (0)
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#else
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/*
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* dummy tlb and user structures.
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*/
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#define v3_tlb_fns (0)
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#define v4_tlb_fns (0)
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#define v4wb_tlb_fns (0)
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#define v4wbi_tlb_fns (0)
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#define v6_tlb_fns (0)
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#define v3_user_fns (0)
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#define v4_user_fns (0)
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#define v4_mc_user_fns (0)
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#define v4wb_user_fns (0)
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#define v4wt_user_fns (0)
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#define v6_user_fns (0)
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#define xscale_mc_user_fns (0)
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#endif /*__ASSEMBLY__*/
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#endif /* _ASMARM_PGTABLE_H */
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