4355082149
This adds Freescale SAI ASoC Audio support. This implementation is only compatible with device tree definition. Features: o Supports playback/capture o Supports 16/20/24 bit PCM o Supports 8k - 96k sample rates o Supports master and slave mode. Signed-off-by: Alison Wang <b18965@freescale.com> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
114 lines
3.1 KiB
C
114 lines
3.1 KiB
C
/*
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* Copyright 2012-2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __FSL_SAI_H
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#define __FSL_SAI_H
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#include <sound/dmaengine_pcm.h>
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#define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
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SNDRV_PCM_FMTBIT_S20_3LE |\
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SNDRV_PCM_FMTBIT_S24_LE)
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/* SAI Transmit/Recieve Control Register */
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#define FSL_SAI_TCSR 0x00
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#define FSL_SAI_RCSR 0x80
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#define FSL_SAI_CSR_TERE BIT(31)
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#define FSL_SAI_CSR_FWF BIT(17)
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#define FSL_SAI_CSR_FRIE BIT(8)
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#define FSL_SAI_CSR_FRDE BIT(0)
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/* SAI Transmit Data/FIFO/MASK Register */
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#define FSL_SAI_TDR 0x20
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#define FSL_SAI_TFR 0x40
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#define FSL_SAI_TMR 0x60
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/* SAI Recieve Data/FIFO/MASK Register */
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#define FSL_SAI_RDR 0xa0
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#define FSL_SAI_RFR 0xc0
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#define FSL_SAI_RMR 0xe0
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/* SAI Transmit and Recieve Configuration 1 Register */
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#define FSL_SAI_TCR1 0x04
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#define FSL_SAI_RCR1 0x84
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/* SAI Transmit and Recieve Configuration 2 Register */
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#define FSL_SAI_TCR2 0x08
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#define FSL_SAI_RCR2 0x88
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#define FSL_SAI_CR2_SYNC BIT(30)
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#define FSL_SAI_CR2_MSEL_MASK (0xff << 26)
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#define FSL_SAI_CR2_MSEL_BUS 0
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#define FSL_SAI_CR2_MSEL_MCLK1 BIT(26)
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#define FSL_SAI_CR2_MSEL_MCLK2 BIT(27)
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#define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27))
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#define FSL_SAI_CR2_BCP BIT(25)
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#define FSL_SAI_CR2_BCD_MSTR BIT(24)
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/* SAI Transmit and Recieve Configuration 3 Register */
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#define FSL_SAI_TCR3 0x0c
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#define FSL_SAI_RCR3 0x8c
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#define FSL_SAI_CR3_TRCE BIT(16)
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#define FSL_SAI_CR3_WDFL(x) (x)
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#define FSL_SAI_CR3_WDFL_MASK 0x1f
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/* SAI Transmit and Recieve Configuration 4 Register */
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#define FSL_SAI_TCR4 0x10
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#define FSL_SAI_RCR4 0x90
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#define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16)
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#define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16)
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#define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8)
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#define FSL_SAI_CR4_SYWD_MASK (0x1f << 8)
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#define FSL_SAI_CR4_MF BIT(4)
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#define FSL_SAI_CR4_FSE BIT(3)
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#define FSL_SAI_CR4_FSP BIT(1)
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#define FSL_SAI_CR4_FSD_MSTR BIT(0)
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/* SAI Transmit and Recieve Configuration 5 Register */
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#define FSL_SAI_TCR5 0x14
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#define FSL_SAI_RCR5 0x94
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#define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24)
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#define FSL_SAI_CR5_WNW_MASK (0x1f << 24)
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#define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16)
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#define FSL_SAI_CR5_W0W_MASK (0x1f << 16)
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#define FSL_SAI_CR5_FBT(x) ((x) << 8)
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#define FSL_SAI_CR5_FBT_MASK (0x1f << 8)
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/* SAI type */
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#define FSL_SAI_DMA BIT(0)
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#define FSL_SAI_USE_AC97 BIT(1)
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#define FSL_SAI_NET BIT(2)
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#define FSL_SAI_TRA_SYN BIT(3)
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#define FSL_SAI_REC_SYN BIT(4)
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#define FSL_SAI_USE_I2S_SLAVE BIT(5)
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#define FSL_FMT_TRANSMITTER 0
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#define FSL_FMT_RECEIVER 1
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/* SAI clock sources */
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#define FSL_SAI_CLK_BUS 0
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#define FSL_SAI_CLK_MAST1 1
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#define FSL_SAI_CLK_MAST2 2
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#define FSL_SAI_CLK_MAST3 3
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/* SAI data transfer numbers per DMA request */
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#define FSL_SAI_MAXBURST_TX 6
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#define FSL_SAI_MAXBURST_RX 6
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struct fsl_sai {
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struct clk *clk;
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void __iomem *base;
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bool big_endian_regs;
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bool big_endian_data;
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struct snd_dmaengine_dai_dma_data dma_params_rx;
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struct snd_dmaengine_dai_dma_data dma_params_tx;
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};
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#endif /* __FSL_SAI_H */
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