2b77933c28
To make the page tables compact, we were using 32-bit PGDs and PMDs.
We only had to support <= 43 bits of physical addresses so this was
quite feasible.
In order to support larger physical addresses we have to move to
64-bit PGDs and PMDs.
Most of the changes are straight-forward:
1) {pgd,pmd}_t --> unsigned long
2) Anything that tries to use plain "unsigned int" types with pgd/pmd
values needs to be adjusted. In particular things like "0U" become
"0UL".
3) {PGDIR,PMD}_BITS decrease by one.
4) In the assembler page table walkers, use "ldxa" instead of "lduwa"
and adjust the low bit masks to clear out the low 3 bits instead of
just the low 2 bits during pgd/pmd address formation.
Also, use PTRS_PER_PGD and PTRS_PER_PMD in the sizing of the
swapper_{pg_dir,low_pmd_dir} arrays.
This patch does not try to take advantage of having 64-bits in the
PMDs to simplify the hugepage code, that will come in a subsequent
change.
Signed-off-by: David S. Miller <davem@davemloft.net>
159 lines
4.6 KiB
C
159 lines
4.6 KiB
C
#ifndef _SPARC64_PAGE_H
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#define _SPARC64_PAGE_H
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#include <linux/const.h>
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#define PAGE_SHIFT 13
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#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
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#define PAGE_MASK (~(PAGE_SIZE-1))
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/* Flushing for D-cache alias handling is only needed if
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* the page size is smaller than 16K.
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*/
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#if PAGE_SHIFT < 14
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#define DCACHE_ALIASING_POSSIBLE
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#endif
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#define HPAGE_SHIFT 23
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#define REAL_HPAGE_SHIFT 22
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#define REAL_HPAGE_SIZE (_AC(1,UL) << REAL_HPAGE_SHIFT)
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#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
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#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
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#define HPAGE_MASK (~(HPAGE_SIZE - 1UL))
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#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
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#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
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#endif
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#ifndef __ASSEMBLY__
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#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
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struct pt_regs;
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extern void hugetlb_setup(struct pt_regs *regs);
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#endif
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#define WANT_PAGE_VIRTUAL
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extern void _clear_page(void *page);
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#define clear_page(X) _clear_page((void *)(X))
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struct page;
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extern void clear_user_page(void *addr, unsigned long vaddr, struct page *page);
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#define copy_page(X,Y) memcpy((void *)(X), (void *)(Y), PAGE_SIZE)
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extern void copy_user_page(void *to, void *from, unsigned long vaddr, struct page *topage);
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/* Unlike sparc32, sparc64's parameter passing API is more
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* sane in that structures which as small enough are passed
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* in registers instead of on the stack. Thus, setting
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* STRICT_MM_TYPECHECKS does not generate worse code so
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* let's enable it to get the type checking.
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*/
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#define STRICT_MM_TYPECHECKS
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#ifdef STRICT_MM_TYPECHECKS
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/* These are used to make use of C type-checking.. */
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typedef struct { unsigned long pte; } pte_t;
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typedef struct { unsigned long iopte; } iopte_t;
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typedef struct { unsigned long pmd; } pmd_t;
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typedef struct { unsigned long pgd; } pgd_t;
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typedef struct { unsigned long pgprot; } pgprot_t;
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#define pte_val(x) ((x).pte)
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#define iopte_val(x) ((x).iopte)
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#define pmd_val(x) ((x).pmd)
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#define pgd_val(x) ((x).pgd)
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#define pgprot_val(x) ((x).pgprot)
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#define __pte(x) ((pte_t) { (x) } )
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#define __iopte(x) ((iopte_t) { (x) } )
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#define __pmd(x) ((pmd_t) { (x) } )
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#define __pgd(x) ((pgd_t) { (x) } )
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#define __pgprot(x) ((pgprot_t) { (x) } )
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#else
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/* .. while these make it easier on the compiler */
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typedef unsigned long pte_t;
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typedef unsigned long iopte_t;
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typedef unsigned long pmd_t;
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typedef unsigned long pgd_t;
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typedef unsigned long pgprot_t;
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#define pte_val(x) (x)
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#define iopte_val(x) (x)
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#define pmd_val(x) (x)
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#define pgd_val(x) (x)
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#define pgprot_val(x) (x)
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#define __pte(x) (x)
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#define __iopte(x) (x)
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#define __pmd(x) (x)
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#define __pgd(x) (x)
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#define __pgprot(x) (x)
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#endif /* (STRICT_MM_TYPECHECKS) */
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typedef pte_t *pgtable_t;
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/* These two values define the virtual address space range in which we
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* must forbid 64-bit user processes from making mappings. It used to
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* represent precisely the virtual address space hole present in most
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* early sparc64 chips including UltraSPARC-I. But now it also is
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* further constrained by the limits of our page tables, which is
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* 43-bits of virtual address.
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*/
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#define SPARC64_VA_HOLE_TOP _AC(0xfffffc0000000000,UL)
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#define SPARC64_VA_HOLE_BOTTOM _AC(0x0000040000000000,UL)
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/* The next two defines specify the actual exclusion region we
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* enforce, wherein we use a 4GB red zone on each side of the VA hole.
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*/
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#define VA_EXCLUDE_START (SPARC64_VA_HOLE_BOTTOM - (1UL << 32UL))
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#define VA_EXCLUDE_END (SPARC64_VA_HOLE_TOP + (1UL << 32UL))
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#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_32BIT) ? \
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_AC(0x0000000070000000,UL) : \
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VA_EXCLUDE_END)
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#include <asm-generic/memory_model.h>
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#define PAGE_OFFSET_BY_BITS(X) (-(_AC(1,UL) << (X)))
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extern unsigned long PAGE_OFFSET;
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#endif /* !(__ASSEMBLY__) */
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/* The maximum number of physical memory address bits we support, this
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* is used to size various tables used to manage kernel TLB misses and
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* also the sparsemem code.
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*/
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#define MAX_PHYS_ADDRESS_BITS 47
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/* These two shift counts are used when indexing sparc64_valid_addr_bitmap
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* and kpte_linear_bitmap.
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*/
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#define ILOG2_4MB 22
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#define ILOG2_256MB 28
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#ifndef __ASSEMBLY__
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#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET)
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#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
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#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
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#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr)>>PAGE_SHIFT)
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#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
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#define virt_to_phys __pa
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#define phys_to_virt __va
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#endif /* !(__ASSEMBLY__) */
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#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#include <asm-generic/getorder.h>
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#endif /* _SPARC64_PAGE_H */
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