95d6791b4f
Define maps for HSMMC devices. S3C2443 has one HSMMC device with base address 0x4A800000. S3C2416 has HSMMC0 at 0x4AC00000 and HSMMC1 at 0x4A800000. So suppose that S3C2443 has only HSMMC1. Define clock for hsmmc0 device and register it. Signed-off-by: Yauhen Kharuzhy <jekhor@gmail.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
120 lines
3.2 KiB
C
120 lines
3.2 KiB
C
/* arch/arm/mach-s3c2410/include/mach/map.h
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*
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* Copyright (c) 2003 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410 - Memory map definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MAP_H
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#define __ASM_ARCH_MAP_H
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#include <plat/map-base.h>
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#include <plat/map.h>
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#define S3C2410_ADDR(x) S3C_ADDR(x)
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/* USB host controller */
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#define S3C2410_PA_USBHOST (0x49000000)
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/* DMA controller */
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#define S3C2410_PA_DMA (0x4B000000)
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#define S3C24XX_SZ_DMA SZ_1M
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/* Clock and Power management */
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#define S3C2410_PA_CLKPWR (0x4C000000)
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/* LCD controller */
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#define S3C2410_PA_LCD (0x4D000000)
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#define S3C24XX_SZ_LCD SZ_1M
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/* NAND flash controller */
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#define S3C2410_PA_NAND (0x4E000000)
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/* IIC hardware controller */
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#define S3C2410_PA_IIC (0x54000000)
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/* IIS controller */
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#define S3C2410_PA_IIS (0x55000000)
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/* RTC */
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#define S3C2410_PA_RTC (0x57000000)
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#define S3C24XX_SZ_RTC SZ_1M
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/* ADC */
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#define S3C2410_PA_ADC (0x58000000)
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/* SPI */
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#define S3C2410_PA_SPI (0x59000000)
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/* SDI */
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#define S3C2410_PA_SDI (0x5A000000)
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/* CAMIF */
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#define S3C2440_PA_CAMIF (0x4F000000)
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#define S3C2440_SZ_CAMIF SZ_1M
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/* AC97 */
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#define S3C2440_PA_AC97 (0x5B000000)
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#define S3C2440_SZ_AC97 SZ_1M
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/* S3C2443/S3C2416 High-speed SD/MMC */
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#define S3C2443_PA_HSMMC (0x4A800000)
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#define S3C2416_PA_HSMMC0 (0x4AC00000)
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#define S3C2443_PA_FB (0x4C800000)
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/* S3C2412 memory and IO controls */
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#define S3C2412_PA_SSMC (0x4F000000)
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#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
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#define S3C2412_PA_EBI (0x48800000)
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#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000)
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/* physical addresses of all the chip-select areas */
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#define S3C2410_CS0 (0x00000000)
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#define S3C2410_CS1 (0x08000000)
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#define S3C2410_CS2 (0x10000000)
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#define S3C2410_CS3 (0x18000000)
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#define S3C2410_CS4 (0x20000000)
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#define S3C2410_CS5 (0x28000000)
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#define S3C2410_CS6 (0x30000000)
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#define S3C2410_CS7 (0x38000000)
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#define S3C2410_SDRAM_PA (S3C2410_CS6)
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/* Use a single interface for common resources between S3C24XX cpus */
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#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
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#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
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#define S3C24XX_PA_DMA S3C2410_PA_DMA
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#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
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#define S3C24XX_PA_LCD S3C2410_PA_LCD
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#define S3C24XX_PA_UART S3C2410_PA_UART
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#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
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#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
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#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
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#define S3C24XX_PA_IIS S3C2410_PA_IIS
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#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
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#define S3C24XX_PA_RTC S3C2410_PA_RTC
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#define S3C24XX_PA_ADC S3C2410_PA_ADC
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#define S3C24XX_PA_SPI S3C2410_PA_SPI
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#define S3C24XX_PA_SDI S3C2410_PA_SDI
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#define S3C24XX_PA_NAND S3C2410_PA_NAND
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#define S3C_PA_FB S3C2443_PA_FB
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#define S3C_PA_IIC S3C2410_PA_IIC
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#define S3C_PA_UART S3C24XX_PA_UART
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#define S3C_PA_USBHOST S3C2410_PA_USBHOST
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#define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0
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#define S3C_PA_HSMMC1 S3C2443_PA_HSMMC
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#define S3C_PA_WDT S3C2410_PA_WATCHDOG
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#define S3C_PA_NAND S3C24XX_PA_NAND
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#endif /* __ASM_ARCH_MAP_H */
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